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May 17, 2010 12:32 PM  says:

Good to know. 

Jun 10, 2010 12:42 PM  says:

Hi there!

 

I am working on option ROM development and I was wondering if you could suggest where I can get a motherboard with the following requirements for my development work.

1. JTAG connector ( so that I can use it with an Arium or any other JTAG based debugger)

2. UEFI bios (since my optionROM will be both legacy and UEFI)

3. atleast 1 PCIe slot (x1, x4,x8 or x16)

 

Thanks in advance.

 

Regards,

Sai

Jun 10, 2010 4:39 PM brian_ami brian_ami  says:

Sai: one of the Intel embedded development platforms would work. The QM57 board might be a good fit, check with an Intel rep.

Jun 16, 2010 2:56 AM  says:

Brian,

 

Thanks for the info. Great stuff. One question, the old post PCI boards use to use a write to port 80 to output checkpoint codes. What is the mechanism for the using the USB debug port to output checkpoint codes? Especially before the port can be setup (ie: very early boot).

 

Thanks!

Jul 21, 2010 12:39 PM brian_ami brian_ami  says:

@mark_k - The USB Debug Port can be setup very early, long before the main USB ports are setup by BIOS. The AMIDebug Rx device I mentioned is an example of how this debug port can be used by BIOS. In AMI Aptio, this device is initialized at the end of the SEC phase (very early, close to the reset vector, prior to memory detection).

 

This whitepaper on Intel EDC might help explain it better ... Improving BIOS Debugging Using USB 2.0 Methods

Jul 27, 2010 12:57 AM  says:

Hi Brian,

    Thanks the scenarios for debugging bios. One question, there's a yellow mark with the PCIE ethernet devece in device manager on win7, how can I debug it? (if I force install the driver for this network device, the yellow mark will disappear, but if I reset the system, it turns out again, I checked the asl and there's no asl code for this network device). 

 

Aug 11, 2010 6:32 AM Lazze Lazze  says:

Hi, hope someone out there can help! I am developing a custom BIOS for an Atom N270 Board with the ICH7, 945GSE chipset, and are having some issues using the shadow RAM. 

 

The problem is to enable shadow RAM for the BIOS. It seems that the PAM area is somehow locked, so even though I enable it for writing and copy the BIOS to the region it will hang as soon as I enable the region for read again. It is evident that, the BIOS was not copied to the shadow area, as when I use caching it will work until the cache is refilled (i.e. as long as there is proper BIOS code in the cache).

 

There are no information of the PAM region in the BIOS guides and the standard documentation states that PAM registers has RWL/RO attributes. PAM registers on previous chipset had RW/RO. So a lock feature has been added and this is a good thing for protection against root kits . However, for a BIOS vendor the lacking information on the PAM registers is crucial as the BIOS has to be in shadow ram to be able to modify  internal data  to run time conditions during POST.

 

Our Intel contact recommended this forum - so if anyone can help, it would be very much appreciated!

 

Aug 9, 2011 3:58 AM vardhan reddy vardhan reddy  says:

hai

 

can anyone tell about what are the hardware initilization will be done by BIOS and how BIOS program can  read by processor of power on reset

(my intention is if BIOS reside inside of SPI falsh when system power on how processor can access this without configuring the PCH SPI interface)