The latest high-end processors in the Intel® Architecture (IA) family have a host of performance-oriented features such as the return of Intel® Hyper-Threading Technology and a wide execution engine. And certainly the memory architecture is among the most important features on the Intel® Xeon® 5500 Processor series that uses the microarchitecture code named Nehalem. Several such processors are part of the company's embedded family, and have allowed partners such as GE Intelligent Platforms (GE Fanuc)* to develop communication platforms that can be optimized for cost and/or performance. The key is the memory controller integrated in the 5500 series – a first for an Intel CPU.


Previously, Intel's high-end CPUs have relied on a memory controller integrated in the so-called Northbridge IC. But Nehalem introduced the Intel® QuickPath Architecture that includes a dedicated memory controller for each processor and the new Intel® QuickPath Interconnect for I/O and interprocessor communications. See this recent article for more background. The Nehalem memory controller can support 3 separate memory channels to DDR3 memory and the architecture offers 3.5 times the memory bandwidth of prior platforms.


Embedded design teams working on a Nehalem-based design should carefully consider the choice of how many memory channels to use. At first glance you might think that more channels are always better although this may also equate to higher costs. But it turns out that the best performance choice between two and three channels also depends on applications.




























Consider the GE Fanuc Intelligent Platforms A100200 AdvancedTCA (ATCA) single-board computer. The ATCA board can host dual- or quad-core processors and as much as 64 Gbytes of memory. The product targets applications such as control plane functions in WiMAX or LTE (Long Term Evolution) 4G wireless base stations.


In developing the A100200, GE Fanuc set out to compare the relative benefits of two or three channel memory configurations. The company settled on a two-channel design for the product based on the target communications application.


It turns out that three channels, as you might expect, offers greater memory transaction rates than a two-channel design. But the design choice is more complicated than raw transaction rates. You also must consider the total number of DIMMs and therefore total memory in the system. Moreover you must analyze the relative importance of transaction rates relative to the number memory page definitions that are simultaneously active in the memory controller.


The GE Fanuc analysis compared memory configurations based on the Intel-recommended configuration where each channel has an equal number of memory DIMMs, and that each channel employed a dual-rank DIMM. That effectively means that you can't compare equivalent total memory sizes, because maximum-populated two and three channel implementations will total different memory capacity. But the conclusion is that a two-channel design provides the best tradeoff in terms of cost and performance. The fact is that the two-channel design can host more total memory than a three channel design and more importantly more active memory page definitions.


GE Fanuc has an excellent whitepaper focused on maximizing memory resources that describes their analysis of Nehalem-based systems. You have to register to download the document, but registration is free.


Don't misunderstand. Three channels, or even one channel, might be best for your design. Some applications will work well spreading static data structures across three channels and taking advantage of the transaction rate advantage. An application such as a wireless base station has very high levels of I/O traffic and benefits from large number of active memory segments and fewer instances where the memory controller must activate a new memory segment.


Have you worked with Nehalem and made a choice on memory configuration? How many channels were best in your application? What else would you like to know about the Nehalem memory architecture? Please share your experience via a comment so that fellow followers of the Intel® Embedded Community can learn from your experience.


Maury Wright

Roving Reporter (Intel Contractor)

Intel® Embedded Alliance


*GE Intelligent Platforms is an Associate member of the Intel® Embedded Alliance.