The embedded systems industry is in a perpetual state of uncertainty as users constantly demand higher performance and all the latest features. A typical embedded product may require multiple hardware and/or software updates over its life to keep up with these demands. Designers worry that a sudden new performance requirement could force a circuit upgrade or even complete redesign. Addressing these concerns, the latest Sandy Bridge microarchitecture from Intel® provides designers a modular and expandable framework that will reduce the system component count and power dissipation while simplifying future updates. Let’s take a look at the inner workings of this new architecture to discover how you may employ it to extend the life, or “future proof”, your next embedded design.

 

Sandy Bridge is the codename for the second generation Intel® Core™ processor family microarchitecture soon to be released to production using the latest 32nm process technology. This new architecture combines a variable number of CPU cores, an integrated graphics processor, Last Level Cache (LLC), and a system agent/memory controller that all communicate using a scalable on-die ring interconnect  system (see figure below). This high speed ring interconnect enables cores and the graphics processor to easily share the cache and memory controller. This ring concept is the key technology behind the Sandy Bridge scalability, allowing Intel® to adjust the number of cores and deliver variants that optimize cost, performance, and power requirements depending on the application.  Embedded designers can select a version that not only covers current requirements but leaves room for future performance enhancements.

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Intel® has also developed a new instruction set called Advanced Vector Extensions (AVX) for Sandy Bridge. AVX is backward compatible with previous x86 ISA (Instruction Set Architecture) extensions and is optimized for vector and scalar data sets such as those found in embedded signal processing applications. The AVX data path has been increased to 256 bits and is well suited for demanding floating point applications. With this extended processing power, embedded designers can boost performance and possibly replace external dedicated DSPs or FPGAs with AVX code to reduce the component count and lower overall power requirements. With embedded signal processing algorithms programmed in AVX code, future requirements changes may be made with a software modification.

 

The integrated graphics processor allows designers to spice up their embedded products with enhanced graphics and video to greatly improve the user interface and easily react to future updates. The graphics processor features an array of parallel execution units for 3D applications and hardware acceleration for high speed encoding/decoding of high definition video.  All of the CPU cores in Sandy Bridge, including the graphics core, support Intel® Turbo Boost Technology, allowing clock frequencies to scale up temporarily to handle intense workloads.

 

The System Agent for Sandy Bridge includes a dual-channel DDR3 memory controller, the Power Control Unit (PCU), 16 PCI-Express 2.0 lanes, Direct Media Interface (DMI), and the display engine. The System Agent connects to the rest of the Sandy Bridge system via the ring interconnect to provide a high-bandwidth, low-latency interface to DRAM and I/O. The PCU is a programmable microcontroller responsible for power and thermal management throughout the chip. The System Agent provides a flexible I/O configuration allowing embedded designers to easily activate functionality as requirements change.

 

Sandy Bridge also supports an advanced version of Intel®’s vPro technology for security and remote system management. This technology allows designers to activate, reconfigure, and if necessary, deactivate a remote embedded system. Intel® Active Management Technology (Intel® AMT), a vital subset of vPro, includes certificate-based security allowing remote access to the embedded system for management and security tasks even when the system is powered off. This technology gives embedded device support personnel a low cost technique to perform remote diagnostics, deliver product training, and manage future software updates.

 

Although there is no guarantee that you will never have to make hardware changes, Sandy Bridge offers embedded designers a highly integrated architecture that promises to boost performance, reduce power needs, and lower recurring system costs. With this flexibility and a little forethought, design teams can hone in on that elusive “future-proof” product. You can find more information about Sandy Bridge in embedded applications from the Troy Willes presentation at IDF. What tips and suggestions can you offer designers to help deal with the inevitable post-delivery requirements changes? Please share your experience and questions via comments with fellow followers of the Intel® Embedded Community. And stand by for more on the Sandy Bridge microarchitecture as I continue this series with information about digital signage and gaming applications along with details on embedded system I/O design and flexibility.

 

Warren Webb
OpenSystems Media®, by special arrangement with Intel® Embedded Alliance