We’re less than a month away from the annual Las Vegas Consumer Electronics Show (CES) and the expected arrival of Intel® Architecture (IA) processors based on the new Sandy Bridge microarchitecture. The better news for embedded systems designers is that they will also get access to the Sandy Bridge architecture in short order. And the second generation of the Intel® Core™ processor family will include numerous enhancements such as ECC memory support, improved Intel® Turbo Boost Technology, and a new set of SIMD instructions called Advanced Vector Extensions (AVX) that will prove very valuable for segments of the embedded market.

 

Let’s start with ECC or Error Correction Code technology that is useful, and in some cases required, for mission critical applications such as those depicted below. ECC technology allows a system to detect and correct what are called soft errors where a data bit is inadvertently flipped from one state to another.

ECC_applications.jpg

 

DRAM memory can be susceptible to soft errors. The term soft error is used because there is no permanent damage to the memory cell. Rather the change in a bit cell is caused by a single-event upset. Possible causes include alpha particles, cosmic rays, thermal neutrons and other radiation sources.

 

Many applications aren’t impacted by soft errors. For example, such a bad bit would not be noticeable in a graphics image or video stream. Most PCs don’t require ECC.

 

Embedded applications in the military, aerospace, financial, medical, gambling, and telecommunication segments often utilize

ECC. Such applications require higher levels of data integrity and guaranteed system uptime, and ECC helps enable those attributes.

 

The Sandy Bridge ECC technology will be capable of detecting and correcting one bad bit in a memory word, or detecting two bad bits in a word. Like the prior-generation Nehalem microarchitecture, Sandy Bridge integrates the memory controller on the processor IC. The ECC implementation will require that eight additional data signals and one additional data strobe be added to the 64-bit memory bus.

 

ECC support will not be in every Sandy Bridge processor. Embedded designers will find support in all of the Sandy Bridge processors shipped in BGA 1023 packages that are derived from processors developed for the mobile space. ECC will also be supported on processors in LGA packages that are derived from processors developed for the workstation space.

 

While ECC is focused at data security, other new features push the performance bar. For example, Intel has significantly enhanced Turbo Boost Technology. The first-generation Turbo Boost Technology allowed one core on a multiple core processor to temporarily run at a clock frequency above the rated frequency. As I covered in a Turbo Boost post earlier this year, the concept allows a core to temporarily apply additional processing power to a compute-intensive task. The first-generation Turbo Boost technology essentially allowed the overclocking of one core so long as the processor was within TDP (thermal design power) limits from the total chip perspective.

 

Second-generation Turbo Boost technology will provide a much more significant performance boost. Multiple processor cores will now be able to operate at an extended frequency. Moreover the graphics subsystem that’s integrated on chip is part of the story (see figure below). When the task at hand is graphics intensive, the frequency of the graphics processor can be ramped for better performance. When the task at hand is compute intensive the TDP headroom goes to one or more processor cores.

 

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Another performance improvement comes in the form of the AVX instruction set. Intel has a long history in supporting math-intensive applications with a specialized SIMD (single instruction multiple data) instruction set. The company has developed four prior generations of SSE (Streaming SIMD Extensions) instructions that augment the baseline X86 instruction set. Moreover processors that support the SSE instructions have hardware-accelerated blocks designed to execute the instructions.

 

The AVX extensions will increase the compute power significantly. While the Nehalem SSE used 128-bit SIMD registers, AVX will utilize 256-bit registers. The extension supports floating point applications. Moreover AVX introduces a new three-operand instruction format that does not overwrite one of the source operands with results.

 

AVX will allow an IA processor to handle DSP-oriented functions that have previously required a companion FPGA or DSP-oriented coprocessor. Examples include medical imaging and telecommunications. In many communications applications, equipment vendors will be able to scale performance purely with off-the-shelf Sandy Bridge processors rather than designing custom data-path silicon. And while the AVX technology is just coming to market, it has been discussed since 2008 and there

is already support for the instructions in operating systems such as Windows and Linux.

 

There’s a lot more to Sandy Bridge and even the topics covered here are worthy of a deeper dive. After the products launch expect to hear a lot more about the enhancements.

 

Have you started thinking about a Sandy Bride design? Do you use ECC in your systems? How have you implemented ECC support in the past and what are your plans going forward? Please share your experience with fellow followers of the Intel® Embedded Community through comments.

 

Maury Wright

Roving Reporter (Intel Contractor)

Intel® Embedded Alliance