• E3815 custom board truble

    I developed board on E3815. But I can't boot it.. please review my trouble: 1. I have minnow turbo and successfully made coreboot custom bios for it (with DCT, fsl and other). I add print POST code to debug uart - an...
    last modified by zhgulev
  • Access Intel Serial IO I2C ES controller...

    We add a DS1371 which is a I2C slave device. Our system is Windows 10. On our system, this device should be connected to Intel Serial IO I2C ES controller. As I know, the host controller should enumerate all slave dev...
    last modified by Tonie
  • How to create a coreboot boot loader for a Juniper Hill CRB?

    Hello,   I have an Oxbow Hill CRB and a Juniper Hill CRB, and I created a coreboot boot loader (SPI Flash Image) with Intel's Reference Proof of Concept Coreboot for Apollo Lake (566288).   The release no...
    last modified by jieli4
  • Intel Apollo Lake Android Marshmallow Question

    Hi, I read document '571613_IntelAtom_E3900_ApolloLake_I_Android_ReleaseNotes_Rev1_6.pdf' and follow this guide. I build android Marshmallow  successful and boot on Leaf Hill CRB.   It show warning mess...
    last modified by angelochen
  • How to bring up new Apollo Lake platform?

    Hi ,   I am trying to bring up a new Apollo Lake-based platform with a coreboot+SeaBIOS combination - it is very similar to the Leaf Hill CRB so I adapted my platform code using the Leaf Hill project as base. I s...
    last modified by Tahnia
  • Cherry Trail Z8750 USB3.0 xhci Compatibility USB3.0 flash issue on Android 7.1

    Hello, We are facing an issue that Cherry Trail Z8750 USB3.0 xhci root hub has USB3.0 flashes compatibility issue while Android 7.1 boots up. some of usb3.0 flashes 100% cannot be recognized while Android 7.1 boots u...
    last modified by Ethan_Ma
  • Broadwell-DE FITC tool request

    Hi, I am trying to bring up my Broadwell-DE(D1507 stepping V2) and I already have coreboot.rom with u-boot payload. I need Grangevill FITC spi flash tool to generate 16MB image.bin. Is someone can tell me where I can...
    last modified by Hilbert
  • Skylake U MSR 0x121 documentation

    Hi, I'm working with firmware code and would like to confirm ACPI Timer Emulation configuration. Which document is relevant to check how to configure that MSR?   Best Regards, Piotr Król
    last modified by pietrushnic
  • Purley FITC tool

    Hello,   I'm built the open sourced[1] Purley MiniPlatform BIOS and I want to flash it onto the device. Can someone tell me where I can find the FITC tool for the platform?   [1] - GitHub - tianocore/edk2-...
    last modified by hristomihaylov
  • XL710 on ARM64 architecture

    Hello,   I started to work on our new GPON embedded platform. HW is not available yet, but I want to be prepared. The board will have a Freescale's Layerscape processor LS2088 with 8 ARM64 cores. It will be conn...
    last modified by cebula
  • Broadwell-DE GPIO have support legacy interrupt ?

    Intel Broadwell-DE GPIO have support legacy interrupt ? if not , how can we use it for interrupt source by external devices.   Thanks.
    last modified by aaron_yang_go
  • PMC feature bits (Intel Flash Image Tool)

    Hi Guys,     Does anyone know what "PMC feature bits" is about?   "PMC Feature enable bits." MISC_PMC_ENABLE.FUNC_DIS_RTC_SAVE_ENABLE value_list="DISABLE_FUNC_DIS_RTC_SAVE,,ENABLE_FUNC_DIS_RTC_SAVE"...
    last modified by hsiaolee
  • Where I can find BCT 3.1.3 ?

    According to release notes of Bay Trail Gold 004 and MR5 supported BCT version is 3.1.3, but on GitHub last available version seems to be 3.2.0. Where I can get 3.1.3 ?   Also prepared packages are available onl...
    last modified by pietrushnic
  • FSP for Skylake (E3-1500 v5 and 6th Gen)

    Hi all, I checked FSP released on GitHub almost 2 years ago and in Release Notes I see that it say:   This Intel® Firmware Support Package (Intel® FSP) release is specifically targeted for 6 th Gener...
    last modified by pietrushnic
  • PMC Controller

    Dear all, I have programmed APM controller in 8-series PCH to move to soft-off sleep state. But now it has been moved to Bus 0, Device 31 and Function 2.Below is the code for moving to soft-off sleep state upto X99 PC...
    last modified by rvmuhilan1978
  • Problems with Bay trail BIOS

    Hello,   I use for a industrial application a PC with Celeron J1900 - memory 4Go - SSD 128Go and BIOS Bay Trail. This PC is installed with Windows 10 and the insdustrial application use a data base. When the a...
    last modified by LeDD
  • Flash descriptor and read/write permissions

    I'm trying to understand flash descriptor and read/write permissions that can be configured using master region. I'm using MinnowBoard Turbot B and trying to change flash descriptor so it will have any effect in my Li...
    last modified by pietrushnic
  • i210

    we programmed the i210 iNVM with the “i210_Invm_SerdDesKX_NoAPM_v0.6.txt” Therfore we got the ID 157C we expected the ID 1536. What is the difference?   We don’t find any tool to program the M...
    last modified by M.Str
  • BIOS not outputing 720x1280 on Apollo Lake displayport

    Hi Guys,   I have a question regarding to display through DP during BIOS POST. I got a 720x1280 MIPI panel for a project and I'd like to make it as default display with my Apollo Lake board (N3350). I got a DP ...
    last modified by hsiaolee
  • Changelog of latest microcodes delivery from 08th of January

    Hello, I wish to know what issues are fixed by the latest microcode dellivery from 08th of January as listed here: Download Linux* Processor Microcode Data File (Has it anything to do with Meltdown/Spectre issue ?)...
    last modified by PatrickA