The original CompactPCI® architecture is based on a parallel bus which connects the system slot to the peripheral slots. The CompactPCI® bus makes it possible to mix 32-bit- und 64-bit-assemblies, though in the last instance the parallel bus limits the data rate. For this reason, the AGP interface (Accelerated Graphics Port) has been especially developed for graphics applications as a fast parallel point-to-point connection. AGP has not been implemented in CompactPCI and is only used on the boards. For multiprocessing CPUs on peripheral slots are controlled via non-transparent bridges. With these bridges certain memory areas can be shared so that they can communicate. However, the software overhead required for this is considerable. There are no standard solutions.
A CompactPCI® extension - PICMG 2.16 – introduced Ethernet on the backplane as another transmission medium beside the parallel PCI bus. This way each board could communicate with the other assemblies over two Ethernet links via a special switch board, so that for multiprocessing the software problem was solved. The Ethernet signals were led to the J3 connector making PICMG 2.16 only applicable for 6U boards.
CompactPCI® Express finally turns away completely from the parallel PCI bus and is based exclusively on PCI Express as a fast serial point-to-point connection. Ethernet was not taken into account. Legacy CompactPCI® plug-in boards are connected via a bridge board. The routing of the PCI Express links can be controlled via switch boards. Like for Legacy CompactPCI®, special, non-transparent PCI Express Bridges with special software requirements are needed for multiprocessing.
CompactPCI® evolves further. The architecture adapts to modern chipsets. The proven mechanics of the IEC 1101 are adopted. Existing boards can be continued to be used. CompactPCI® in conjunction with the extensions PlusIO and Plus is a future-safe platform for industrial computers.