Standard Backplanes for CompactPCI Plus (PICMG CPlus.0)

Version 1

    Author: Andreas Lenkisch, Principal Engineer Backplanes, Schroff GmbH

     

    PICMG CompactPCI Plus (CPLUS.0) brings CompactPCI into the world of the serial interfaces offered by today's chipsets.

     

    In designing the specification, particular importance was given to two factors. The existing CompactPCI ecosystem - the hardware and the knowledge and experience gained by engineers - should be adopted as widely as possible. Secondly, interfaces such as PCI Express, serial ATA, USB and Ethernet Base-T should all be available in the system simultaneously, rather than on an either-or basis. This considerably increases flexibility and makes much elaborate coding unnecessary, but it does require a large number of plug contacts in the system slot connector. This problem has been solved with the choice of the AirMax VS connector from FCI/Amphenol, which also satisfies a number of other requirements pertaining to CompactPCI Plus connectors.

    Despite the large number of connections however a 6U CPU is required. The serial interfaces can already all be provided to the system on a 3 U CPU in full bandwidth and distributed by the backplane.

    1 PCIe 16x link

    7 PCIe 4x links

    8 SATA

    8 USB (1&2)

    8 USB (3)

    8 Ethernet Base-T (10/100/1000/10G)

    The backplane connects the CPU system slot to up to 7 peripheral slots with equal priority and also connects a predefined slot to a 16x PCIe link for high-performance or graphical applications.

    Ethernet is set up as full mesh between the maximum of 9 slots of a standard backplane, thus allowing very simple grouping of CPUs for high processing power.

     

    The peripheral slots are equipped only with one connector with 6 rows (J1/P1). This is sufficient for power, control signals and the communications interfaces. The 16x link requires a second connector (2J/2P). Ethernet is connected via a separate connector (J6/P6).

     

    The connector positions on the peripheral slots that do not carry signals, J2/P2 to J5/P5 or J3/P3 to J5/P5, may be used for rear I/O.

     

    The standard backplane to be available from stock from system providers will initially be a 9-slot version. This is effectively the maximum number of slots that can be supported where all interfaces must be available on each peripheral slot in full bandwidth. "Smaller" backplanes can be simply derived from this design and will soon be added to the portfolio as required.

     

    Since project-specific solutions do not require all interfaces on every slot, a splitting of the storage interface (SATA) from the PCIe/USB/Ethernet section, for example, is conceivable. The PCIe link can also however be divided into individual lanes (1x).

     

    Thus a system can be built without bridges that has 16 slots (8x SATA + 8x PCIe/USB/Ethernet) or with up to 8x SATA, 8x USB/Ethernet and 44x PCIe slots.