PCI Express Configuration Possibilities with CompactPCI PlusIO

Version 1

    Author: Manfred Schmitz, CTO MEN Mikro Elektronik


    CompactPCI® PlusIO – PICMG 2.30 – permits to lead a total of four PCI Express interfaces to the backplane. The Ultra Hard Metric connectors on the plug-in board permit data rates of up to 5 Gb/s, traditional 2-mm connectors being usable on the backplane.


    These four interfaces (also called links) can be used to control four PCI Express-based peripheral boards. Each interface is equipped with one differential receive pair and a differential transmit pair – a lane. The four PCI Express lines can e.g. be compatible to CompactPCI® Express or to CompactPCI® Plus.


    Each interface reaches data rates of 250 MB/s with PCI Express Gen1 or 500 MB/s with PCI Express Gen2 per direction. For some applications, however, e.g. for image processing, these data rates are still not sufficient. For this reason, the PICMG Standard 2.30 CompactPCI® PlusIO allows to "cluster" the four PCI Express interfaces. This way, the four links with one lane each defined for PICMG 2.30 can also be configured as two links with two lanes each or even as one link with four lanes. In the last-mentioned case, theoretical data rates of 1000 MB/s with PCI Express Gen1 or 2000 MB/s for Gen2 can be reached, but only with a connected device.


    The PICMG 2.30 CPU board imports the configuration via four control lines which are also used to activate the respective 100 MHz clock which is allocated to a PCI Express interface. No additional lines are necessary. This way, CompactPCI® PlusIO PICMG 2.30 guarantees high flexibility for the connection of high-speed peripheral components based on PCI Express while being 100\% compatible to the established CompactPCI® standard and without needing additional infrastructure like switches or bridges – a future-safe solution.