COM Express gains a major interoperability boost

Version 3

    Jeff Munch Column


    COM  Express gains a major interoperability boost

    New PICMG Carrier Design Guide (CDG) enables carriers that work with  multiple vendors' modules

    If you have struggled to get your  carrier board working with a second COM Express module, or have held off  designing due to the buzz about the issues involved, good news has  arrived. More than a dozen leading suppliers have set aside their  differences to collaborate for a year on a design guide aimed at module  interoperability. PICMG is publishing the Carrier Design Guide (CDG)  this fall with critical information and example circuits to improve your  module sourcing options.


    Hammer time
    The CDG contains reference schematics and explanations to help  implement common peripherals on unique carrier board designs. In some  cases, this means terminating a module's integrated I/O. Otherwise, PC  architecture buses such as PCI Express, PCI, LPC, and SMBus can be  extended to support other peripherals and standard expansion slots on  the carrier board. CDG complements the COM.0 specification for COM  Express modules. It does not replace or obsolete COM.0. However, it  reinforces many of the details of COM.0, and acts as a "hammer" to  enforce ongoing module consistency.


    Merging onto the  Express Lane
    The general-purpose PCI Express lanes can be  grouped (x1, x4, and sometimes x2) in combinations that total six lanes.  These are Southbridge lanes, not the x16 PCI Express Graphics (PEG)  interface from the Northbridge. The CDG reinforces the COM.0 order for  using (filling) lanes. In addition, the CDG shows how to handle PCI  Express (PCIe) clock buffering when more than one PCIe device or slot is  used on the carrier, and what signals to connect for hot swap of slot  cards. You will also learn about advanced features like SDVO and ADD2  cards in detail. High-speed differential pair signals require special  routing considerations, and the CDG offers handy guidelines.


    Power  management
    The industry-standard Advanced Configuration and  Power Interface (ACPI) specification defines power-saving levels when  the system is not operating. Implementation across COM Express modules  has been inconsistent in the past. The CDG addresses this point by  defining the on/off state of up to eight power rails (nets) that may be  present in the system, including the separate standby rails that are  powered when the main rails are at zero volts. In addition, suspend  status signals and wake up events are defined more thoroughly. The CDG  describes how to provide power to peripherals so that they continue to  operate as desired during the suspect and soft off states. After all,  these peripherals and part of the Southbridge must stay awake while the  rest of the system is off, otherwise the system won't wake up without a  complete re-boot


    Free to be legacy-free?
    Standard desktop connectors like SATA, LAN, and USB seem innocuous,  given that the signals are "free" in the chipset and in standard  controllers. But taking into consideration such things as USB  over-current and Ethernet transformer tap voltage consistencies will  quickly dispel a carrier designer's overconfidence with these circuits.  The CDG delves into these topics with enough detail to design a working  carrier the first time.


    A contentious topic is how to  implement serial ports and other "legacy" peripherals within an  architecture that is touted as "legacy-free." The CDG does an important  job of warning designers about the limited "supported" usage of the Low  Pin Count (LPC) bus for such peripherals. Initialization of carrier LPC  devices is heavily intertwined with the BIOS on each vendor's module.  Instead, designers are advised to use the dynamic driver-loading  plug-and-play model of USB, PCI, and PCI Express devices for serial  ports and other legacy ports.


    The CDG also contains a  wealth of "fine points" pertinent to  designs. Such information can make  the difference between a carrier that operates and one that doesn't.  Among the details drilled into are:

    • Coupling  capacitors
    • Bypass capacitor types
    • Bulk capacitance on  power and standby rails
    • Pull-up resistor values
    • Series  and parallel terminations
    • Ferrite beads
    • Reset circuits
    • Strapping  options


    A word to the wise
    Finally, a  bit of caution is in order. While the CDG is thorough in providing  designs for interchangeability of COM Express modules, it is absolutely  essential to use each module vendor's documentation in order for carrier  boards to be designed properly. There is no substitute for proven  design methodologies. Designers without much PCI Express experience  would be wise to leverage the combined experience of the module and  carrier designers who contributed to CDG. Finally, what is not supported  or recommended is as important to know as what is supported.


    Although  it will take some time for the consistencies presented by CDG to ripple  through participating vendors' modules, there is no question that PICMG  has served the industry well in the publication of this new document.


    Jeff  Munch is Chair of the  AdvancedTCA  subcommittee and also CTO of ADLINK  Technology. Mr. Munch  has more than  twenty years experience in the  hardware design, software  development,  and engineering resource  management. Before joining ADLINK,  Mr. Munch  spent five years at  Motorola Computer Group as Director of  Engineering,  and previously, 9  years as vice president of engineering at Pro-Log.