Author: Manfred Schmitz, CTO MEN Mikro Elektronik
A standard PC supports graphics. A modular computer based on the PICMG CompactPCI Serial specification CPCI-S.0 shall also be able to control displays.
Many – also high-performance – chipsets have a built-in graphics controller today. As a rule, the CPU and graphics controller share the main memory in this architecture. This way, cost-effective and well-fitting solutions can be achieved for low to medium requirements especially in the 2D area. If displays with a very high resolution are to be controlled, the performance both of the CPU and of the graphics unit are limited by the bandwidth of this shared memory. If you want to operate several high-resolution displays at the same time or if you have higher requirements regarding the graphics itself (e.g., 3D rendering), it is advisable to use an external, independent graphics controller with its own video memory.
If you choose an external graphics controller, the data transfer rate of the connection between the chipset and the graphics controller is the critical factor for the performance. For this reason, this connection has promoted modern buses. The development first of the PCI bus, then the AGP bus and finally PCI Express was pushed on decisively by graphics cards.
Contrary to other serial interconnects such as SATA and USB 3.0 for example, PCI Express is not limited to a single lane (a differential receive and transmit signal line pair) but combines up to 16 of these lanes in parallel to control the graphics card (PCI Express x16). As it is relatively frequent that more than one graphics card has to be controlled, all common chipsets and graphics controllers support a mode which splits the PCI Express x16 link into two PCI x8 interfaces. This splitting halves the maximum burst data rate. This is compensated for, however, by the constant advancement of the transmission frequency at the PCI Express interface (called Gen1, Gen2, Gen3 etc).
Graphics extensions are one reason for the special CompactPCI Serial architecture. Two slots are connected to the system slot via PCI Express x8 interfaces. This way, two peripheral slots of the CompactPCI Serial system can be equipped with high-performance graphics cards. This works with standard backplanes without additional measures like switched fabrics, i.e. without additional costs and loss of performance.
Otherwise all peripheral slots have identical characteristics, the remaining slots being connected via a PCI Express x4 interface. Principally, graphics cards can be plugged into every peripheral slot. The performance is not quite as high there, but still sufficient for many applications.
Modern graphics chips (e.g., from ATI) are able to control up to four high-resolution displays simultaneously via DisplayPort. A CompactPCI Serial system can accommodate up to eight graphics cards (without bridges), making it possible to control 32 displays with the corresponding software.
This extensibility of graphics functions shows that the CompactPCI Serial CPCI-S.0 architecture is very well suited for applications which far extend the possibilities of the parallel CompactPCI. For example, control rooms of power stations, railway control centers, even video walls consisting of more than 32 monitors can now be equipped with CompactPCI Serial systems.