CSoC Platform / Digital Subsystem IP for IoT

Version 1

    CSoC

    CSoC (Configurable SoC) is a SoC development platform comprising of a Digital Subsystem IP and infrastructure which enables rapid prototyping of SoCs for IoT edge devices. Digital subsystem IP is a digital platform built from a digital IP bouquet comprising of 16+ general purpose IPs (peripheral, platform, wireless connectivity, bus infrastructure and memory subsystem) which drives architecture of IoT edge devices. The design IPs are designed with comprehensive, configurable and scalable feature-set to meet diverse product requirements and can be easily customized to adapt to any on-chip bus architecture with appropriate bus wrappers. Given the requirements specification of the IPs aligned with product requirements, IPs can be configured yet optimized for area, power and performance. The digital subsystem IP is processor agnostic and be integrated with any processor core (ARM, ARC, MIPS etc.) of choice with appropriate compute intensity as dictated by the product requirements.

     

    The platform also provides adaptive SoC verification environment built with native System Verilog / custom VIPs for rapid integration and SoC verification. The implementation (ASIC & FPGA) flow flush scripts and environments for the IPs and the digital subsystem which are part of the platform enables rapid prototyping. Test reuse methodology, cohesive HW - SW development, ease of 3rd party IP integration and automation utilities enables faster integration and development reducing time to market significantly.

     

    For rapid and successful product development of IoT edge devices IDMs, OEMs, platform solution providers (SIP solutions) can boot strap their SoC development with CSoC framework and digital subsystem IP customization / enhancements, 3rd party IP integration (digital / analog) and using the adaptive SoC verification environment to realize the SoC. The OS / RTOS, drivers and relevant SW stacks can be developed, integrated in parallel with the cohesive development strategy. The SoC can be further be FPGA prototyped, emulated at application levels before ASIC realization takes-off and the CSoC platform is highly conducive for such a collaborative effort and parallel executions.