1 Reply Latest reply on Dec 22, 2015 7:41 AM by gabriel.thomas

    Haswell DDR3 trace impedance question

    PVWB Brown Belt

      We are about to re-spin a Haswell based design of ours.

      We wanted to be absolutely sure that the information in

      Intel Doc 486711486712 has not been updated in a later,

      different document.  It has a lot of layout information

      but we mostly wanted to verify that for UDIMM use

      (one per channel) we should use 62 Ohm differently pairs

      (As described on.pdf page 88 of this doc)
      and 40 Ohm single-ended signals. (As described

      on .pdf page 90 of this document)

       

      Thanks, Paul.

        • Re: Haswell DDR3 trace impedance question
          gabriel.thomas Brown Belt

          Hello Paul,

           

           

          Welcome back to the Intel Embedded Community.

          Please refer to the latest document, 486711, Design Guide

          Take into consideration that the Differential Trace Impedance applies for regions D and E.

          Resistance is 62 ohms for each channel. ( UDIMM ). Refer also to figures 4-9 and 4-10, to see how  these regions are distributed.


          For Single Ended Trace Impedance for regions D and E are 40 ohms for each channel (UDIMM), and 40 ohms only for channel B when regions are  F and G.

           

          I hope this information helps.

           

           

          Regards,

           

          Gabriel Thomas