Welcome back to the Intel Embedded Community.
Please refer to the latest document, 486711, Design Guide
Take into consideration that the Differential Trace Impedance applies for regions D and E.
Resistance is 62 ohms for each channel. ( UDIMM ). Refer also to figures 4-9 and 4-10, to see how these regions are distributed.
For Single Ended Trace Impedance for regions D and E are 40 ohms for each channel (UDIMM), and 40 ohms only for channel B when regions are F and G.
I hope this information helps.