11 Replies Latest reply on Sep 26, 2016 8:47 AM by SABARIVASA@ECIL

    coreboot hangs at post code 19 on Bayley Bay

    Kathappan Community Member

      Hi all,

       

      When I try coreboot on Bayley Bay platform along with fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015), it is getting hang at post code 19.

       

      Also I tried with debug version fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG) , it still at that point and below is the debug log.

       

      I have flashed the last 2 MB region with coreboot image upon 8 MB vendor bios.


      coreboot gives the control to FSP binary service routine(FspInitApi) and it is getting hang when trying to do PCH initialize(PchMiscInit) inside FSP part code.

       

      POST 19 code info : EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_ENTRY ==> Clock Init PEIM Entry

       

      I have not seen the clock related setting available when customizing fsp binary using BCT.

       

      I tried to disable south cluster component such as EMMC,HSUART,SATA and SIO using BCT , it didn't help me.

       

      Can anyone please help me provide some inputs such as related below to proceed further debugging on it ?

      1. Any other setting we can try out using BCT

      2. About devices configuration to be initialized byPchMiscInit function.

      3. Anything need to be cared/double checked from coreboot side in order to giving control to FspInitApi function.

      4. Does pch straps settings may cause this since I am using upper 6 MB region flash data which is from vendor bios.

      4. Please suggest anything on it.

       

      Thanks in advance,

      Kathappan

       

      <<<<<<<<<<<<                Start                          >>>>>>>>>>>>>>>

       

      coreboot-coreboot-unknown Thu May 12 08:04:42 UTC 2016 romstage starting...

      RTC Init

      POST: 0x44

      POST: 0x47

      POST: 0x48

      Starting the Intel FSP (early_init)

      PM1_STS = 0x0 PM1_CNT = 0x0 GEN_PMCON1 = 0x44000

      prev_sleep_state = S5

      Configure Default UPD Data

      PcdMrcInitSPDAddr1:             0xa0 (default)

      PcdMrcInitSPDAddr2:             0xa2 (default)

      PcdSataMode:            0x01 (set)

      PcdLpssSioEnablePciMode:                0x01 (default)

      PcdMrcInitMmioSize:             0x800 (default)

      PcdIgdDvmt50PreAlloc:           0x02 (default)

      PcdApertureSize:                0x02 (default)

      PcdGttSize:             0x02 (default)

      SerialDebugPortAddress:         0x3f8 (default)

      SerialDebugPortType:            0x01 (default)

      PcdMrcDebugMsg:         0x01 (default)

      PcdSccEnablePciMode:            0x01 (default)

      IgdRenderStandby:               0x00 (default)

      TxeUmaEnable:           0x00 (default)

      PcdOsSelection:         0x04 (default)

      PcdEMMC45DDR50Enabled:          0x01 (default)

      PcdEMMC45HS200Enabled:          0x00 (default)

      PcdEMMC45RetuneTimerValue:              0x08 (default)

      PcdEnableIgd:           0x01 (default)

      AutoSelfRefreshEnable:          0x00 (default)

      APTaskTimeoutCnt:               0x00 (default)

      GTT Size:               2 MB

      Tseg Size:              8 MB

      Aperture Size:          256 MB

      IGD Memory Size:        64 MB

      MMIO Size:              2048 MB

      MIPI/ISP:               Disabled

      Sdio:                   Enabled

      Sdcard:                 Enabled

      SATA:                   Enabled

      SIO Dma 0:              Enabled

      SIO I2C0:               Enabled

      SIO I2C1:               Enabled

      SIO I2C2:               Enabled

      SIO I2C3:               Enabled

      SIO I2C4:               Enabled

      SIO I2C5:               Enabled

      SIO I2C6:               Enabled

      Azalia:                 Enabled

      SIO Dma1:               Enabled

      Pwm0:                   Enabled

      Pwm1:                   Enabled

      Hsuart0:                Enabled

      Hsuart1:                Enabled

      Spi:                    Enabled

      Lpe:                    Disabled

      eMMC Mode:              eMMC 4.5

      SATA Mode:              AHCI

      Xhci:                   Enabled

      POST: 0x92

       

       

      ============= PEIM FSP  (VLYVIEW0 0x00000304) =============

      Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE

      Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3

      Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A

      The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0

      Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39

      Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38

      Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

      Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389

       

       

      Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480

      Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1

       

       

      Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39

      Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FD4

      The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000

       

       

      Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926

      PcdMrcInitTsegSize = 8

      PcdMrcInitMmioSize = 800

      PcdMrcInitSPDAddr1 = A0

      PcdMrcInitSPDAddr2 = A2

      Setting BootMode to 0

      Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56

      Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE

      About to call MrcInit();

      BayleyBay Platform Type

      RID = 0x11.

      Reg_EFF_DualCH_EN = 0x40030040.

      CurrentMrcData.BootMode = 4

      C1.D0: SPD not present.

      Configuring Memory Start...

      START_RMT:

                               RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight CmdLeft CmdRight

      ------------------------------------------------------------------------------------------------

      Channel 0 Rank 0         -22       21       -21     19     -25       26          0       0

      STOP_RMT:

      CMD module is per channel only and without Rank differentiation

      Configuring Memory End

      UpperTotalMemory =  0x80000000

      dBMBOUND         =  0x80000000

      dBMBOUNDHI       =  0x80000000

      dGFXBase         =  0x7BE00000

      dTSegBase        =  0x7B000000

      Save MRC params.

      Current MRC Data DDR Freq    1

      Current MRC Data Core Freq   1

      Current MRC Data Tcl         7

      Current MRC Data WL          6

      Current MRC Data DDRType     1

      Current MRC Data MMIO Size   800

      Current MRC Data TSeg Size   8

      Channel 0

              Enabled 1

       

       

               Socket 0

                      DimmPresent 1

                      DimmDataWidth 1

                      DimmBusWidth 3

                      DimmSize 2

                      DimmSides 0

      Channel 1

              Enabled 0

       

       

               Socket 0

                      DimmPresent 0

                      DimmDataWidth 0

                      DimmBusWidth 0

                      DimmSize 0

                      DimmSides 0

      Current MRC Timing Data MRC_DATA_TRP     7

      Current MRC Timing Data MRC_DATA_TRCD     7

      Current MRC Timing Data MRC_DATA_TRAS    13

      Current MRC Timing Data MRC_DATA_TWR   8

      Current MRC Timing Data MRC_DATA_TWTR   4

      Current MRC Timing Data MRC_DATA_TRRD    4

      Current MRC Timing Data MRC_DATA_TRTP   4

      Current MRC Timing Data MRC_DATA_TFAW   1B

      PeiInstallPeiMemory MemoryBegin 0x7AE00000, MemoryLength 0x200000

      Old Stack size 24576, New stack size 131072

      Heap Offset = 0x0 Stack Offset = 0x840F0000

      Stack Hob: BaseAddress=0x7AE00000 Length=0x20000

       

       

      Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3

      Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A

      Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

      Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE

      Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFC1281

       

       

      Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731

      Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7

       

       

      Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F

       

       

      InstallVlvInitPpi() - Start

      Register PPI Notify: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3

      InstallVlvInitPpi() - End

       

       

      InstallPchInitPpi() - Start

      PmcBase needs to be programmed and enabled before here.

      ProgramGpioSCForSDCardWA Done....

      Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D

      Register PPI Notify: 00B710BA-8CD6-4BF3-AB7A-9A24F54CC334

      Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE

      Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7AFCB3C4

      PchModPhyProgramming() - Start

      SOC B0 and later ModPhy Table programming

      PchModPhyProgramming() - End

      PchSataInit() - Start

      PchSataInit() - End

      InstallPchInitPpi() - End

       

       

      Register PPI Notify: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6

       

       

      Register PPI Notify: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5

      Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793

      Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B

       

       

       

       

      Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C

       

       

      Install PPI: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3

      Notify: PPI Guid: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3, Peim notify entry point: 7AFDE2E9

      VlvInitPeiEntryPoint start....

       

       

      ------------------------ VLV SSA Platform Policy dump Begin ---------------

      Graphics Configuration:

      GttSize : 2 MB

      IgdDvmt50PreAlloc : 2

      PrimaryDisplay : 0

      ApertureSize : 2

      Turbo Enable : 1

       

       

      ------------------------ VLV SSA Platform Policy dump END -----------------

      ProgramEcBase Done....

      SSASafeConfiguration Done....

      Clear Dbuff  to all zero before read 0xFFFFFFFF

      PUNIT_ISPSSPM0 value is 0x3000003

      ISP Device is enabled by fuse

      Skip ISPConfig

      InitThermalRegisters Done....

      IGD enabled.

      IGD Turbo Enable.

      PUNIT_BIOS_CONFIG11 = 0x400301C0.

      PUNIT_BIOS_CONFIG22 = 0x40030140.

      TotalMmioLength:   0x10400000 bytes

      GraphicsInit Done....

      Install PPI: 09EA8911-BE0D-4230-A003-EDC693B48E11

      Install mVlvPeiInitPpi Done....

      Install PPI: 15344673-D365-4BE2-8513-1497CC07611D

      Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry point: 7AFCBB94

      PchInitialize() - Start

      PchMiscInit() - Start

       

      <<<<<<<<<<<<<<<<<<                      end                       >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

        • Re: coreboot hangs at post code 19 on Bayley Bay
          Carlos_A Brown Belt

          Hello Kathappan ,

           

          Thank you for contacting the Intel Embedded Community.

           

          We have received your consultations and we are working to answer them as soon as possible.

           

          Thanks in advance for your patience and understanding.

           

          Best Regards,

          Carlos_A.

          • Re: coreboot hangs at post code 19 on Bayley Bay
            AdolfoS Brown Belt

            Hello Kathappan

             

            Could you please clarify the following statement:

            Kathappan E wrote:

             

            I have flashed the last 2 MB region with coreboot image upon 8 MB vendor bios.

             

             

            Why are you mixing to bios binaries on a single chip?

             

            Is there any issue if you use the original BIOS of the Bayley Bay?

             

            Are you including TXE firmware in your platform?

             

            I will be waiting for your feedback.

             

            Best Regards,

            Adolfo Sanchez

              • Re: coreboot hangs at post code 19 on Bayley Bay
                Kathappan Community Member

                Hi Adolfo,

                 

                Sorry for the delay. Before going to answer your questions, I share some info.

                 

                First I am new to learn about coreboot source. So, I choose the FSP binary to build coreboot and make a trial on Intel board. I have one Bayley Bay custom board (not a CRB) which is based Atom E3825 and D0 stepping SoC.

                 

                Why are you mixing to bios binaries on a single chip?

                Actually , I tried with 2 MB coreboot and it is not even getting detectedand I meant it is hang at postcode 00.

                After some research I come to know it is required TXE and flash descriptor to proceed but don't have TXE and descriptor binary to add and make 8 MB flash image along with coreboot.  But I have vendor BIOS (8 MB) which has TXE and flash descriptor. Hence, I updated coreboot image upon it to boot it.

                 

                Is there any issue if you use the original BIOS of the Bayley Bay?

                No issues faced. It is booting fine.

                 

                Are you including TXE firmware in your platform?

                I believe, it has been included since I am using  upper 6 MB from vendor bios.

                 

                Can you please help me to provide inputs to proceed further ?

                 

                Thanks,

                Kathappan

                  • Re: coreboot hangs at post code 19 on Bayley Bay
                    AdolfoS Brown Belt

                    Hello Kathappan

                     

                    This is not the proper way to merge your BIOS with the coreboot.rom image.

                     

                    Here are the options that you could try

                    1) You can try is using the Intel FPT tool to replace the BIOS section of the SPI with your own .rom image (you need to make sure to unlock your BIOS before performing this step)

                    2) You can download the Intel TXE and create your own .bin file using the FITC tool, the disadvantage of this method is that you will need to configure the description region and the TXE  by yourself.

                    3)This is similar to the first option the difference is that you should ask your BIOS vendor if they have a tool to update the BIOS (some vendors provide those tools).

                     

                    The FITC and FPT tools come together with the TXE image that can be downloaded here: https://edc.intel.com/Link.aspx?id=9982

                     

                    But you need to have a Privilege Account to download it, you can apply here for privilege access: http://www.intel.com/content/www/us/en/forms/design/registration-privileged.html

                     

                    Additionally what tool are you using to program the .rom image on your SPI?

                     

                    Best Regards,

                    Adolfo.

                      • Re: coreboot hangs at post code 19 on Bayley Bay
                        AdolfoS Brown Belt

                        Hello Kathappan

                         

                        I have and additional option that might be useful for your case, the only thing that you need is to have the original .bin file from your BIOS vendor.

                         

                        You use the ifdtool that comes included with the coreboot package to extract the file descriptor and the txe binaries from your bios .bin file, then you merge them in your coreboot image.

                         

                        You can find more information on the following link: http://wiki.minnowboard.org/Coreboot#Intel.C2.AE_Firmware_Support_Package_.28Intel.C2.AE_FSP.29

                         

                        On the section TXE and SPI descriptor.

                         

                        Please note that the site is strictly for Minnowboard, you might need to rename the file me.bin instead of txe.bin depending on your coreboot version.

                         

                        I hope this information is useful for your case.

                         

                        Best Regards,

                        Adolfo Sanchez.

                          • Re: coreboot hangs at post code 19 on Bayley Bay
                            Kathappan Community Member

                            Hi Adolfo,

                             

                            Thanks for your comments and sorry for the late reply. Here is consolidated points form my side.

                             

                            1) You can try is using the Intel FPT tool to replace the BIOS section of the SPI with your own .rom image (you need to make sure to unlock your BIOS before performing this step)

                            I will try to get FPT and check on it.

                             

                            2) You can download the Intel TXE and create your own .bin file using the FITC tool, the disadvantage of this method is that you will need to configure the description region and the TXE  by yourself.

                            I am checking to get privileged access.

                             

                            3)This is similar to the first option the difference is that you should ask your BIOS vendor if they have a tool to update the BIOS (some vendors provide those tools).

                            As of now, I am unable to contact them and will try get it later.

                             

                            Additionally what tool are you using to program the .rom image on your SPI?

                            I am using Dediprog SF100.

                             

                            Extracting descriptor bins using ifdtool

                            I tried same to extract the Vendor BIOS image (8 MB) and I got the below map and binaries.

                             

                              Flash Region 0 (Flash Descriptor): 00000000 - 00000fff

                              Flash Region 1 (BIOS): 00300000 - 007fffff

                              Flash Region 2 (Intel ME): 00001000 - 002fffff

                              Flash Region 3 (GbE): 00fff000 - 00000fff (unused)

                              Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)

                             

                            flashregion_0_flashdescriptor.bin => renamed to descriptor.bin

                            flashregion_1_bios.bin

                            flashregion_2_intel_me.bin => renamed to me.bin

                             

                            Have configured the same in menuconfig and build the 8 MB coreboot image

                             

                            But still source is getting hang at same point (post code 0x19) => PchMiscInit() - Start inside the FSP code.

                             

                            I am not sure that external factors (such asTXE/ME/Descriptor/coreboot) does cause it getting infinite loop(may be timeout) when device initialization (pcie). But I suspect it may due to FSP code. Also I tried latest FSP available in Intel site for bayleybay platform , it didn't help.

                             

                            I would be more useful for me if you give more points.

                             

                            Thanks a lot for your support,

                            Kathappan

                          • Re: coreboot hangs at post code 19 on Bayley Bay
                            SABARIVASA@ECIL Green Belt

                            Dear Adolf,

                             

                            Link  to download FITC and FPT tools is not working. Please provide the working link to download FITC and FPT tools.

                             

                            Thanks