1 of 1 people found this helpful
Thank you for contacting the Intel Embedded Community.
In order to better understand your question, could you please give us the complete part number of the processor related to your design?
Thanks in advance for your cooperation.
I see that I haven't provided you enough information. Sorry. I'll try to fix it.
Processor used in the design is: Intel® Core™ i7-4850EQ (4x1.60GHz, GT3e, 47W)
My eDP display is: Sharp LQ156D1JX01B, connected to DDI2.
I also cannot understand some of points described in "Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet". For example, let's take Table 2-17 "Functional Strap Definitions":
DDPB_CTRLDATA (I'll ise DDPB for screenshots only, real port for my DDI2 is DDPC)
This signal has a weak internal pull-down.
0 = Port B is not detected.
1 = Port B is detected.
From one point of view, I should pull it up in my board. From the other side, in same document:
So, should I pull DDPB_CTRLDATA up or leave it as is, pulled down? It's hard enough to do for each signal, because they exist only on pins of 220-pin 0.5mm pitch connector, so it isn't so simple to solder wires on the pins to check each suggestion like this.
From another point of view, in Skylake EDS, Vol.1, p.2.5 "Display Interfaces", says, without mentioninig about HDMI:
"DDI ports (B, C, and D) are disabled if No Connect Pull-up resistor on following PCH signals: DDPB_CTRLDATA, DDPC_CTRLDATA and DDPD_CTRLDATA accordingly."
I understand that difference between DP and HDMI is only in signal levels, but... how should I consider DDPB_CTRLDATA pin - DisplayPort Aux or HDMI Port B Control Data?
Maybe there is some appnote like "How to attach eDP panel to LynxPoint PCH", or any other document, connected together DisplayPort and CPU (PCH) initialization logics? CPIS spec, mentioned on would be useful in this way, but I cannot find it on Intel's site.
The problem now is that I don't know timing parameters for eDP signals (PWR_OK, eDP_VDD_EN, eDP_BKLTEN, eDP_BKLTCTL, HPD) from CPU side. One that presented is PCH8 specs does not contain this "predefined range of values":
Main thing I need to know: what is time margin for value T1+T2+T5 (max and min values) by default for PCH and what is time period between PCH power on and raise eDP_VDD_EN signal?
1 of 1 people found this helpful
Hello DarkTiger ,
Thanks for your reply.
The default values for the Panel power-up delay and power backlight off to power down delay times are stated on page 81 of the Intel(R) Graphics Media Accelerator – Binary Modification Program (BMP) User’s Guide document # 368119.
On the other hand, reviewing your communications it seems that you are confused because you are mixing the eDP interface and DisplayPort, specifically when you mentioned that the monitor is attached to DDI2, but it does not require eDP_VDD_EN, eDP_BKLTEN, eDP_BKLTCTL , which are exclusive for eDP. In order to clarify, please review the Figure 6, and Tables 33 and 34; on pages 33, 87, and 88 of the Mobile 4th Generation Core, Pentium and Celeron processor family Datasheet Volumen1 document # 328901. Also, It is important to let you know that the eDP is only supported on Intel® 4th Generation Core Mobile (Port A) .
By the way, the Intel(R) Core(TM) i7-4850EQ Processor is unrelated to Embedded devices. Also, the third party designs should be supported by their manufacturers, because Intel ignores the information related to them.
We hope that this information may help you.
Thank you for the answer. A lot of required info, including main thing I need - 600ms delay between PCH and eDP panel power up.
First of all, I need to apologize for using third-party designs for explaining my problem, but I haven't had access to approporiate Intel reference designs for Haswell at that moment. I had to use ones that I found in Internet.
I also think that all Haswell PCH's have same init protocol for display controllers, whether they are for Core Mobile or not. If it is not so, could you move this topic to Hardware section?
Could you please mark my statements which are wrong? It will help me a lot to understand where I should correct the design. Skylake-U 6600 works good with same panel connected to same DDI port on bootstrap, but Haswell doesn't.
1. eDP and DisplayPort data protocols are the same, at least at initialization stage
2. eDP display can be attached to DDI ports on CPU providing that power and backlight signals (enable and PWM) will be implemented by external CPU-independent hardware (this way we lose OS possibilities like display on/off and adjust brightness without additional OS drivers, which I don't need at the moment)
3. If we attach eDP display to DDI port (DDIA, for example), we need to provide HPD interrupt in appropriate time margins after CPU and PCH power is enabled, to let CPU catch HPD interrupt after CPU power is on. Signal eDP_VDD_EN provides right timing interval.
4. When DisplayPort is attached to DDI interface, DisplayPort implements p.3 by pulling HPD signal up after 600ms (pointed in BMP_UG) + "usual" HPD delay after CPU + PCH power is up (or, what is the same, since 3.3V establishes at pin 20 (DP_PWR) on DisplayPort cable).
5. Pulling HPD pin on PCH to 3.3V without connection it with HPD line from display involves that both DisplayPort and eDP devices will not detected at all, because there won't happen HPD interrupt as a positive signal transition.
6. If we use DDI port in 'native' mode (not eDP), we don't need to invert HPD signal.
Thank you for advance,