For the I210, what bits need to be set in which registers to get MDIO to talk to the outside of the chip when in SGMII mode? Are there any other requirements for the chip to start talking to the external PHYs?
We are unable to get the I210 to talk MDIO externally. We have found a few posts on the forum discussing the issue, and in particular the one suggesting setting iNVM word 0x24 to 0x4224, but we are still unable to get any activity on the MDC and MDIO pins of the chip.
Our prototype board has an Intel I210-AS and Marvel 88E6390 switches that we are bringing up. We are using the igb driver in Linux 3.10 with patches from OpenWRT to enable MDIO access, but this is mostly used as a vehicle to get to the registers of the I210 and we are not expecting the driver to work properly until we have adapted it for the Marvel switches.
We have modified the iNVM so that the driver properly detects SGMII mode with external PHY, and the registers look all good when the MDIO transactions happen as far as we can understand, but there is no activity on either the MDC or MDIO pins.
In particular we set word 0x24 to 0x42A4, so both the 2 wires SFP enable and the external MDIO bits are set, and link mode is set to SGMII mode. The DeviceID is set to 0x157C. The destination bit in MDICNFG is set, as can be seen in the register dump attached.
The following is our iNVM image which is based on the I210_Invm_SerDesKX_NoAPM_v0.6.HEX as supplied with Intel's eepromARMtool:
16E80002 00001541 0000001A 08100241 402F1411 34003611 1C605011 157C1A17
05844211 02904817 16D10002 00FF00A8 16D00002 5E000090 15381A11 13000011
00C60211 00000411 42A44811 00000000 00000000 00000000 00000000 00000000
There are a few invalidated words, but these are the registers set by it:
We have hooked up an oscilloscope to pins 55 (SFP_I2C_CLK) and 57 (SFP_I2C_DATA) to verify that MDIO transactions reach outside of the I210, but don't see any activity, even though the driver seems to perform two MDIO transactions, before failing with an MDIO error. (The actual data requested is irrelevant at this stage).
The driver code reads PHY register 2 followed by PHY register 3. It always writes to the PHY page register (0x16) first, and it is page 0 for both these reads. The first read "succeeds" and returns ffff as data. The second read fails (MDI_ERR set in MDIC register) but also returns ffff as data.
It looks like there is nothing responding on the bus, and the lowest address bit of a read is latent on the bus and is shifted in as the first bit of the read, and hence we have a failure when the lowest address bit is non-zero. That is speculation, and also of novelty value as we have no activity on the outside MDIO bus, neither MDC nor MDIO.
What else is required to enable MDIO?
A register dump of the first two MDIO transactions is attached.
i210_sgmii_mdio.txt.zip 3.5 K