Thank you for contacting Intel Embedded Community.
In order to better understand this situation, we would like to address the following questions:
Could you please confirm that your implementation fulfills with the guidelines that are stated as the answers to the questions 2.11, 2.13, 2.28, and 2.29, on pages 9 and 12 of the Intel(R) Ethernet Controller I210/I211 Frequently Asked Questions (FAQs) document # 334026?
Could you tell us the specific Intel(R) Ethernet Controller I210 (such the i210-AS, i210-AT, or i210-IS) is related to this situation?
Could you please confirm if this design has been reviewed by Intel?
Please give us all the information that may answer these questions.
Thanks in advance for your cooperation.
thanks for your reply!
Sorry, for the lack of some information.
The design hasn't been reviewed by Intel, but it is a subset of an earlier working design using i210-IS we did in the past.
If needed, I could provide the schematics - but I think the problem isn't located there.
I know the FAQs document.
2.11 What speeds do the I210/I211 support?
10, 100, 1000 MBit --> We want to use 100 and 1000 MBit, but actually only trying 1000MBit
2.13 What are the PCI Device IDs for the I210/I211?
Depending on the image I program the chip claims to bei 0x1536 (Fiber) / 0x1537 (SerdesKX) / 0x1538 (SGMII)
2.28 The layout guidelines describe the advantages of 85 Ω design
vs. 100 Ω design for the differential traces (PCIe). But for
SerDes, 100 Ω impedance is recommended. Are the same
benefits not also valid for SerDes?
The Design has impedance controlled traces, PCIe 85Ohm and Serdes 100Ohm.
2.29 Is there a way to monitor the GMII interface (between MAC
and PHY) on the I210?
Don't know, in which context this might help? We're not using an external phy connected to i210.
Hope, these informations help you in understanding.
Thanks for your reply.
Based on your previous communication, could you please verify that affected design has been developed based on the guidelines stated in the Intel(R) Ethernet Controller I210-IS Layout Review Checklist document # 495299, Intel(R) Ethernet I210-IS Schematic Reference Design document # 490116, and Intel(R) Ethernet Controller I210 Design Guide document # 513305?
In case that you ignore the answer, please review it based on these documents to avoid any discrepancy with the suggested recommendations.
We hope that this information may help you to solve this inconvenience.
thank you for the links to these documents.
We did our best to fulfill all the these requirements. I don't think it's an HW issue.
Could you please look over the questions in my first post and answer them?
Thanks for your update.
The i210 will support SGMII to another device, but the drivers only support connection to the Marvell 88E1111. Any other device would need a customized driver, which should be developed, tested, and validated by your own.
In case that the switch supports SERDES connection, KX should be the option to use.
The SERDES has only the options KX and BX. This information and more details are stated in section 1.4.2, on page 9 of the Intel(R) Ethernet Controller I210 Datasheet Networking Division (ND) document # 333016.
We hope that this information may help you.