5 Replies Latest reply on Sep 26, 2016 6:37 AM by Carlos_A

    i210 SERDES/SGMII connection to switch

    andrjoer Community Member



      we built up a PCIe card for verification purposes.

      Using an i210 with flash connected to a Marvell switch 88E6122 port 6. OS for testing is WIN7(64). Target OS will be Linux in the future.

      We thought we could use SGMII - because it is the only thing the switch understands on this port. After reading some threads here we realized i210 only supports SGMII with an external PHY. Damn!

      The SERDES_KX image should be used. So we did. Marvell told us to deactivate Autoneg and force speed, link and full duplex. So we did for the switch and adjusted i210 image  "Initialization Control Word 2 (Word 0x0F)" to 0x3600h.

      Lanconf now tells "1GBit full duplex" established, the switch says something like "link up". But no data is transmitted.

      Another info from Marvell was to put i210 in 1000Base-x mode and activate 'bypass' - meaning : detecting sync pattern without auto-neg result in link up 1000 –x

      Not sure, if this is possible-  neither how to do so. Tried the "speed select bypass" bit in  "Extended Device Control Register - CTRL_EXT (0x0018; R/W)" but with no effect.


      Any ideas how to bring up the connection?


      Thanks, Andy

        • Re: i210 SERDES/SGMII connection to switch
          Carlos_A Brown Belt

          Hello andrjoer,


          Thank you for contacting Intel Embedded Community.


          In order to better understand this situation, we would like to address the following questions:


          Could you please confirm that your implementation fulfills with the guidelines that are stated as the answers to the questions 2.11, 2.13, 2.28, and 2.29, on pages 9 and 12 of the Intel(R) Ethernet Controller I210/I211 Frequently Asked Questions (FAQs) document # 334026?


          Could you tell us the specific Intel(R) Ethernet Controller I210 (such the i210-AS, i210-AT, or i210-IS) is related to this situation?


          Could you please confirm if this design has been reviewed by Intel?


          Please give us all the information that may answer these questions.


          Thanks in advance for your cooperation.


          Best Regards,


            • Re: i210 SERDES/SGMII connection to switch
              andrjoer Community Member

              Hello Carlos_A,


              thanks for your reply!

              Sorry, for the lack of some information.


              The design hasn't been reviewed by Intel, but it is a subset of an earlier working design using i210-IS we did in the past.

              If needed, I could provide the schematics - but I think the problem isn't located there.


              I know the FAQs document.

              2.11  What speeds do the I210/I211 support?

              10, 100, 1000 MBit        --> We want to use 100 and 1000 MBit, but actually only trying 1000MBit


              2.13  What are the PCI Device IDs for the I210/I211?

              Depending on the image I program the chip claims to bei 0x1536 (Fiber) / 0x1537 (SerdesKX) / 0x1538 (SGMII)


              2.28 The layout guidelines describe the advantages of 85 Ω design

              vs. 100 Ω design for the differential traces (PCIe). But for

              SerDes, 100 Ω impedance is recommended. Are the same

              benefits not also valid for SerDes?

              The Design has impedance controlled traces, PCIe 85Ohm and Serdes 100Ohm.


              2.29 Is there a way to monitor the GMII interface (between MAC

              and PHY) on the I210?

              Don't know, in which context this might help? We're not using an external phy connected to i210.


              Hope, these informations help you in understanding.


              Regards, Andy