I use coreboot and fsp for initialize braswell n3150, but i have an issue : Failures for postcode 0xBB - failed in the FSP: 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
In the config of coreboot , i don't have microcode update .
In documentation of coreboot :coreboot/Documentation/Intel/SoC/soc.html#TempRamInit
" Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found"
But i downloaded microcode.dat for braswell on intel site. i don't have signature 0x406c3 corresponding in microcode.dat .
if no update for microcode, i have no need integrate microcode in coreboot.rom ? else how to do ?
Thank you for contacting Intel Embedded Community.
Please verify that affected design has implemented the guidelines stated as a reference at the Patch set updated for coreboot: soc/braswell: CPUID for D0 stepping.
We hope that this information may help you.