5 Replies Latest reply on Nov 14, 2016 11:26 AM by Carlos_A

    eMMC in ACPI mode on Baytrail E3845

    ustas Community Member

      Hello.

       

      I have the board with Intel Baytrail E3845 and eMMC card, use coreboot 4.4, seabios 1.9.1, Intel FSP Gold4.

       

      It comes out switch eMMC 4.5 controller to ACPI mode by FSP. If set "Enable PCI mode for SCC devices" (PcdSccEnablePciMode) = Disabled in Binary Configuration Tool (BCT), a controller still a PCI device. Log of FSP DEBUG binary has not changed:

       

      FspNotify(EnumInitPhaseReadyToBoot)

      fsp_header_ptr: fffb0094

      FSP Header Version: 1

      FSP Revision: 3.4

      FSP Got Notification. Notification Value : 0x00000040

      FSP Ready To Boot ...

      Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B

      Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7AF9802F

      PchInitExitBootCallback() Start

      <...>

      ConfigureSccAtBoot() Start

      Using eMMC 4.5

      Overwrite the nslew/pslew -> 0

      ConfigureSccAtBoot() End

      <...>

      PchInitExitBootCallback() End

       

       

      This choice differs from set "Enable PCI Mode for LPSS SIO devices" = Disabled, which the actual switch LPSS to ACPI mode, with reaction in log:

       

      FspNotify(EnumInitPhaseReadyToBoot)

      fsp_header_ptr: fffb0094

      FSP Header Version: 1

      FSP Revision: 3.4

      FSP Got Notification. Notification Value : 0x00000040

      FSP Ready To Boot ...

      Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B

      Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7AF9802F

      PchInitExitBootCallback() Start

      <...>

      ConfigureLpssAtBoot() Start

      Switching LPSS1 DMA into ACPI Mode.

      Switching LPSS2 DMA into ACPI Mode.

      Switching LPSS2 I2C 0 into ACPI Mode.

      Switching LPSS2 I2C 1 into ACPI Mode.

      Switching LPSS2 I2C 2 into ACPI Mode.

      Switching LPSS2 I2C 3 into ACPI Mode.

      Switching LPSS2 I2C 4 into ACPI Mode.

      Switching LPSS2 I2C 5 into ACPI Mode.

      Switching LPSS2 I2C 6 into ACPI Mode.

      Switching LPSS1 PWM 0 into ACPI Mode.

      Switching LPSS1 PWM 1 into ACPI Mode.

      Switching LPSS1 HS-UART 0 into ACPI Mode.

      Switching LPSS1 HS-UART 1 into ACPI Mode.

      Switching LPSS1 SPI into ACPI Mode.

      ConfigureLpssAtBoot() End

      <...>

      PchInitExitBootCallback() End

       

       

      Before posting, I also tried enable SD/SDIO/EMMC 4.41 controllers, disable eMMC 4.5, and had seen in log:

       

      ConfigureSccAtBoot() Start

      Using eMMC 4.41

      Switching SCC SDIO into ACPI Mode.

      Switching SCC SD Card into ACPI Mode.

      ConfigureSccAtBoot() End

       

      But, eMMC still as PCI device.

       

      P.S. Excuse me for "my english".

        • Re: eMMC in ACPI mode on Baytrail E3845
          Carlos_A Brown Belt

          Hello ustas,

           

          Thank you for contacting Intel Embedded Community.

           

          There are actually three UARTS on the Bay Trail SoC – two HSUARTs that are part of the Serial IO (SIO) block of devices, and one legacy UART, that is part of the Platform Controller Unit (PCU) block of devices.

           

          The HSUART registers are accessed through PCI BARs, whereas the legacy UART uses the legacy COM1 I/O space registers, 3f8h-3ffh.

           

          Whether or not they disable the on-chip HSUARTs is irrelevant, as they don’t use the legacy I/O space addresses for COM1 and COM2.

           

          Although you can disable the HSUARTs with the BCT, the legacy UART cannot be enabled or disabled via the BCT. The legacy UART is actually enabled in coreboot - file coreboot/src/soc/intel/fsp_baytrail/romstage/romstage.c calls function byt_config_com1_and_enable(), which is implemented in file coreboot/src/soc/intel/fsp_baytrail/romstage/uart.c and sets the bit to enable the legacy UART (it’s disabled by default when the chip powers on). This could be replaced by code that initializes COM1 on the Fintek part instead of the UART.

           

          Note that the FSP might also enable the legacy UART internally during the call to FspInitEntry. If so, then it would simply need to be disabled again in the continuation function, which, in coreboot, is function romstage_main_continue() located in file coreboot/src/soc/intel/fsp_baytrail/romstage/romstage.c.

           

          Here is the public datasheet for reference on the various UARTs:

          http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-e3800-family-datasheet.pdf

           

          Also, you can review as a reference the Baytrail MMC ACPI mode and Does SeaBIOS support eMMC? forums that may have some information that can help you.

           

          Please let us know if this information is useful to you.

           

          Best Regards,

          Carlos_A.