Thank you for contacting Intel Embedded Comunity.
In order to be better understand your consultation, we would like to address the following questions:
Could you please tell us the part numbers of the Processor and the SPI nvSRAM related to this situation?
Could you please clarify if the affected project is your design or a third party one? In case that it is a third party, please give us all the information related to it.
Could you please give us all the details of the data that you tried to write in the SPI nvSRAM? By the way, how many SPI nvSRAM devices are experiencing this problem?
Please give us all the information related to these questions to have a better idea of this problem.
Hello The specified item was not found..
Thanks for your feedback!
The part numbers of the Processor is E3845, the SPI nvSRAM is Cypress CY14X101PA. And the project is our design.
As so far, there are approximately 10 devices that we have produced are experiencing the problem.
We just test the nvSRAM by writing data to nvSRAM and reading it back; After encountering the problem, we tried to figure out the cause.
As pointed out about, our hw engineer found the signal of data at the wrong data of the above picture is mistake when it came from baytrail spi controller.
What is confusing is that when writing 256 bytes or more bytes data per time, it should experiencing the problem easily, but when wrting 64 bytes or less bytes, it run well.
After searching the intel docs, we found Doc 514482 which has a charpter about "Write Granularity" of SPI controller, but I don't understant it well, it means we must write
less than 64 bytes per time after following a command opcode and a address ? or it means others ?
By the way, our design has a CPLD as a switch for two host machine, but we just run one host machine at testing. The following is the block diagram,
Hello, leon_du :
Thanks for your update and We apologize for the delay to give you an update.
Based on your previous communication, we would like to know if the affected design fulfills with the guidelines stated in the Intel(R) Atom(TM) Processor E3800 Product Family Platform: Design Guide [PDG] document # 512379, specifically the ones stated in section 20 on pages 257, 258, and 259.
It is important to let you know that this PDG is classified as Intel confidential which requires a CDNA between your company and Intel as well as a Privileged EDC account. To request an upgrade from your Basic EDC account to a Privileged account, go to http://www.intel.com/content/www/us/en/embedded/embedded-design-centersupport.html and click on “Manage Your Intel Profile” found in the “Manage Your Account” section of the page. From there you can request an upgrade.
By the way, could you please confirm that your project has been reviewed by Intel? In case that you want to request this service, please follow the instructions stated at the Design Review Services website.
We hope that this information may help you.