16 Replies Latest reply on Mar 10, 2017 8:55 PM by njm

    E3815 custom board truble

    zhgulev Community Member

      I developed board on E3815. But I can't boot it.. please review my trouble:

      1. I have minnow turbo and successfully made coreboot custom bios for it (with DCT, fsl and other). I add print POST code to debug uart - and see it.

      2. when I write my bios (and other ) in my board I see that E3815 read it from flash after reset (CPU is S0 state) and it doesn't do anything. I don't see anything on debug uart..


      I have XDP3 board and I can connect it to my board.. But I can't understand what I can do whit it...


      Please help me..

        • Re: E3815 custom board truble
          Carlos_A Brown Belt

          Hello, zhgulev:


          Thank you for contacting Intel Embedded Community.


          In order to better understand this situation, we need to address the following questions:


          Could you please tell us with the assistance of your BIOS vendor if affected BIOS implementation fulfills the suggestions stated in the Intel(R) Atom(TM) processor E3800-M/D SoC: BIOS Writer's Guides? These documents can be accessed if you have a CDNA between your company and Intel as well as a Privileged EDC account because they are classified as Intel confidential. To request an upgrade from your Basic EDC account to a Privileged account, go to http://www.intel.com/content/www/us/en/embedded/embedded-design-centersupport.html and click on “Manage Your Intel Profile” found in the “Manage Your Account” section of the page. They can be found at:


          Intel(R) Atom(TM) processor E3800-M/D SoC: BIOS Writer's Guide (Volume 1 of 2) document # 514147

          Intel(R) Atom(TM) processor E3800-M/D SoC: BIOS Writer's Guide (Volume 2 of 2) document # 514148

          Intel(R) Atom(TM) SoC E3800-I: BIOS Writer's Guide Addendum document # 526998


          Could you please confirm if the affected design has been implemented based on the Intel(R) Atom(TM) Processor E3800 Product Family Platform: Design Guide (PDG) document # 512379 recommendations? This PDG requires an EDC privileged account to be accessed as well.


          Please give us all the information that may answer the previous questions.


          Thanks for your cooperation to solve this inconvenience.


          Best regards,

          Carlos_A .

          • Re: E3815 custom board truble
            Brett Green Belt



            The boot process of this chip does a lot of things before it releases the x86 core which leads to a lot of confusion. As you have seen, there is a lot of activity to the boot flash but if you look at what is read it is just the descriptor table and the TXE. One thing that seems to have gotten multiple people, including the minnowboard designers, is you must have pull-ups on the SVID_ALERT, SVID_CLK and SVID_DATA lines otherwise the hardware never gets acknowledgement that VCORE is OK and holds the x86 in reset. So while you think the chip is running the part you want is not. JTAG works even if x86 is not. And as you have found out, you must have the TXE loaded to do debugging to the x86 core.


            Intel will do a schematic review for you for free that finds things like this. If you haven't done so already I strongly suggest it.


            Other areas to look at revolve around the RTC. Even if you are not using it you still have to supply a clock to it.


            Let me know if I can be of further assistance.



              • Re: E3815 custom board truble
                njm Green Belt


                Thanks a lot for your advice. We will check it faster as can. At the first blush - all ok.. but we will check it very carefully.

                • Re: E3815 custom board truble
                  njm Green Belt

                  Brett we check SVID lines and found one assembled error.. After corrected it we have had strange result - our XDP3 cant connect to our boadr:


                  E-L-C-CONERR: target connection failure.  E-2201: Unable to connect to target: Target IDCODE does not match the expected value!

                  Please verify the selected scanchain matches the actual target or override this check.

                      Expected: 0x0A69A013 Received:

                  All bits in the expected mask must be set, extra stepping bits are ignored.


                  Why it happened?


                  we continue chek this interface and I hope today I will have access to confidential documentation...

                • Re: E3815 custom board truble
                  njm Green Belt

                  Now I have next situation... Board start .. but memory doesn't work.. I don't see any activity on DDR interface.. I have 8chip in 8bit mode..

                  is there any idiea?

                  I use fsp V4_debug



                  ============= PEIM FSP  (VLYVIEW0 0x00000304) =============

                  Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE

                  Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3

                  Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A

                  The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0

                  Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39

                  Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38

                  Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

                  Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389



                  юInstall PPI: 06E81C58-4AD7-44BC-8390-F10265F72480

                  Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1



                  Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39

                  Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FD4

                  The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000



                  ЬInstall PPI: A55D6970-1306-440C-8C72-8F51FAFB2926



                  ЬPcdMrcInitTsegSize = 8

                  PcdMrcInitMmioSize = 800

                  PcdMrcInitSPDAddr1 = A0

                  PcdMrcInitSPDAddr2 = A2

                  Setting BootMode to 0

                  Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56

                  Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE

                  About to call MrcInit();

                  BayleyBay Platform Type

                  RID = 0x11.

                  Reg_EFF_DualCH_EN = 0x40030040.

                  CurrentMrcData.BootMode = 4

                  Configuring Memory Start...

                  • Re: E3815 custom board truble
                    njm Green Belt

                    according to the document https://deakons.fedorapeople.org/tn4107_power_up_initialization_and_reset.pdf  DRAM0_CKP signal must be set to an active state. But in our design, I can only see the transition DRAM0_DRAMRST# to 1, but I do not see that DRAM0_CKP changes its state. On Minnow DRAM0_CKP becomes active.



                    What can affect the DRAM0_CKP ?

                    • Re: E3815 custom board truble
                      njm Green Belt

                      After I installed 2014SP1 and set threadcount=1. After this I could connect to my board.

                      Now I try configure EDK2 source for compile it fo my board..


                      Are the Anybody now how I can set E3815 profile in EDK (cash size and count cpu core)..