13 Replies Latest reply on Apr 28, 2017 9:33 AM by Carlos_A

    braswell pcie training

    keziaha Green Belt

      i have FPGA device pcie, but i load fpga after enumeration pcie, how to configure braswell for support pcie hot-plug ? or re-launch training pcie ?

        • Re: braswell pcie training
          Carlos_A Brown Belt

          Hello, keziaha:

           

          Thank you for contacting Intel Embedded Community.

           

          In order to implement PCIe hot-plug please use the Slot Capabilities (SLCAP) register specifically the Hot-Plug Capable (HPC) and Hot-Plug Surprise (HPS) bits; and Slot Control; Slot Status (SLCTL_SLSTS) register specifically the Hot-Plug Interrupt Enable (HPE) bit. This information and more details are stated in sections 36.1.18 and 36.1.19; on pages 2421 and 2423 of the N-series Intel® Pentium® Processors and Intel® Celeron® Processors External Design Specification (EDS) – Volume 3 of 3 document # 547871.

           

          We hope that this information may help you.

           

          Best regards,

          Carlos_A.

          • Re: braswell pcie training
            keziaha Green Belt

            Hello Carlos,

             

            we check with fpga team several point before you disturb.

             

            Best regards,

            Sébastien

              • Re: braswell pcie training
                keziaha Green Belt

                We have configured port 1 in hotplug, we haven't no detection, we check with oscilloscope on data pci, no signal of detection.

                In hotplug mode, can you explain pci detection ? can you force pci detection?

                As a reminder, we load fpga(altera cyclone V)after enumeration PCI to do by coreboot. I would like use hot plug detection for see fpga device.

                 

                Best regards,

                Sébastien

                  • Re: braswell pcie training
                    Carlos_A Brown Belt

                    Hello, keziaha:

                     

                    Thanks for your replies.

                     

                    Based on your previous communications, could you answer our communication of the past April 21st, 2017 8:13 AM?

                     

                    Waiting for your answers.

                     

                    Best regards,

                    Carlos_A.

                      • Re: braswell pcie training
                        keziaha Green Belt

                        In response to the mail past April 21st, 2017 8:13 AM:

                         

                        1.I don't have contact with FPGA manufacturer. FPGA is cyclone V with IP standard for pcie.

                         

                        2.our design has been reviewed by Intel.

                         

                        3.For block diagram, i can provide directly, but not through the forum, how to send directly ?

                         

                        Sébastien

                          • Re: braswell pcie training
                            Carlos_A Brown Belt

                            Hello, keziaha:

                             

                            Thanks for your reply.

                             

                            Based on your previous communication, we would like to address the following questions:

                             

                            Could you please clarify if this problem is related to a specific PCIe port or various? In case that you ignore the answer, please try to reproduce this situation on different PCIe ports and let us know the results.

                             

                            Could you please tell us if the affected PCIe ports have issues with other PCIe cards?

                             

                            Could you please let us know the procedure that you have followed to check your Braswell design with the help of Intel? By the way, where do you find the steps to perform this verification?

                             

                            Could you please verify the FPGA implementation with its manufacturer help and let us know the results?

                             

                            Please let us know the information that should answer these consultations to have a better idea of this issue.

                             

                            Waiting for your reply.

                             

                            Best regards,

                            Carlos_A.

                              • Re: braswell pcie training
                                keziaha Green Belt

                                Hello,

                                 

                                In datasheet " 18.2.2.1 Express Card Hot-Plug Events":

                                A full Hot-plug Controller is not implemented.

                                Presence detection occurs when a PCI Express* device is plugged in and power is

                                supplied. The physical layer will detect the presence of the device, and the root port will

                                set the SLSTS.PDS and SLSTS.PDC bits.

                                 

                                if only :

                                SLCAP --> Hot-Plug Capable (HPC) & Hot-Plug Surprise (HPS) is set.

                                SLCTL_SLSTS --> Hot-Plug Interrupt Enable (HPE) & Presence Detect Changed Enable (PDE) is  set

                                 

                                SLSTS.PDS and SLSTS.PDC is set when detection ?

                                But training pcie is executed while detection or we must launch manually training ?

                                 

                                In my case, i have fpga already connected, but not loaded with firmware. i can use hot plug detection, when fpga loaded ?

                                 

                                i tested:

                                set CLIST_XCAP.SI = 1

                                1/ check before  load fpga slsts.pds & slsts.pdc == 1

                                2/ load fpga

                                3/ check after , slsts.pds & slsts.pdc == 1

                                 

                                Why before load fpga pds = 1 ? how to working detection ?

                                 

                                Best Regards

                                Sébastien

                                • Re: braswell pcie training
                                  keziaha Green Belt

                                  Hello, here my answer:

                                   

                                  Based on your previous communication, we would like to address the following questions:

                                   

                                  Could you please clarify if this problem is related to a specific PCIe port or various? In case that you ignore the answer, please try to reproduce this situation on different PCIe ports and let us know the results.

                                   

                                  A---> FPGA is plugged on first pci device port, Port1.We have design an card with braswell & fpga on same PCB. We have other device pci, there is no problem with other device.

                                   

                                  Could you please tell us if the affected PCIe ports have issues with other PCIe cards?

                                   

                                  A---> We have other device pci, there is no problem with other device.

                                   

                                  Could you please let us know the procedure that you have followed to check your Braswell design with the help of Intel? By the way, where do you find the steps to perform this verification?

                                   

                                    A---> i don't have all information, but we have provided electrical diagram for perform verification.

                                   

                                  Could you please verify the FPGA implementation with its manufacturer help and let us know the results?

                                     A---> we have team fpga internal, with a lot of experience.

                                  Please let us know the information that should answer these consultations to have a better idea of this issue.

                                   

                                    Normally, in generic PC, the device PCI is ready before cpu, when we boot. In our case,

                                    our  pci device (fpga) is not ready when we boot.Because there isn't firmware in FPGA.

                                    So, when the cpu launch detection , the fpga device not responding.

                                    For resolve this issue, after loading of firmware in fpga, i have 2 solutions:

                                   

                                    - hot-plug feature: the detection pci is automatically launch by cpu after loading firmware fpga.

                                    For the moment, this way is not working, see message :

                                   

                                   

                                   

                                   

                                    • Re: braswell pcie training
                                      Carlos_A Brown Belt

                                      Hello, keziaha:

                                       

                                      Thanks for your update that we really appreciate.

                                       

                                      Based on your previous communication and since Intel guarantees the proper functionality, such fulfilling the standards listed as supported, of their devices if your design achieves with the suggestion listed in their documentation, the problem with PCIe ports only happens with the FPGA implementation as you mentioned, so it is totally related to the FPGA design.

                                       

                                      Due to this fact, we suggest you as a reference use the support channel that better fit to your needs of the listed at the FPGA manufacturer Support website.

                                       

                                      We hope that this information is useful to you.

                                       

                                      Best regards,

                                      Carlos_A .

                                • Re: braswell pcie training
                                  keziaha Green Belt

                                  Hello Carlos,

                                   

                                  when i set LCTL_LSTS RL bit, i have Link Training (LT) change value to 1 , but when i check to oscilloscope on data line, i don't have signal , no detection, why ?

                                  After LT set : i check in loop:

                                  LCTL_LSTS LT : always 1

                                  PCIESTS1  LTSMSTATE :  always 1

                                  LCTL_LSTS LBMS : always 0

                                   

                                  best regards,

                                  Sébastien

                                   

                                   

                                  SLCAP