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Thanks for your reply
I checked the document.
From the external clock architecture (Figure 24 and 25, page 127, 128), there are no clocks from PCH.
But in Lightning Ridge schematic (SCHEMATIC CDI # 553664, page 417), the clock for M.2 is from PCH when using external clock architecture.
The clocks for other devices are all switched to the external clock source (CK420BQ) when using external clock architecture, except M.2.I still don't know why after studied the document.
Thanks for your patient.
As I know, PCIe interface always needs common clock to ensure the data transfer precision.
In Lightning Ridge, when using isclk(PCH clock), the host(PCH) and device(M.2) are using the same clock source (PCH).
But when using external clock (CK420BQ), the host(PCH) is using the clock from CK420BQ, the device(M.2) is using the clock from PCH.
So I am confusing about this kind of clock topology.
Is M.2 a special PCIe device ?
Or PCH could use isclk and extclk at the time ?