3 Replies Latest reply on Jul 28, 2017 5:49 AM by Carlos_A

    PDG routing guideline trace length question

    Ansonlin Community Member

      The PDG lists a lot of topology of different signals and also has suggestion of total trace length. The trace length usually limits the minimum and maximum length.

      I know why the trace has maximum length limitation but how about the minimum length? Fox example, the USB 2.0 external toplology total trace length is from minimum 3" to maximum 12".

      If the connector is really close to the chip. Do I need to follow minimum 3" limitation by extending the traces?

        • Re: PDG routing guideline trace length question
          Carlos_A Brown Belt

          Hello, Ansonlin :

           

          Thank you for contacting Intel Embedded Community.

           

          In order to better understand your questions, could you please let us know the name and number of the documents, also the part number of the Intel devices associated with this thread?

           

          We really appreciate your help to find the information that should answer your questions.

           

          Best regards,

          Carlos_A.

            • Re: PDG routing guideline trace length question
              Ansonlin Community Member

              Hi Carlos,

               

              The document number is 557775_APL_PDG and you can refer to Table 62. USB 2.0 External Topology Routing Guidelines (with Common Mode Choke and
              ESD Protection Diode).

              It shows "Total Trace Length(USB) is minimum 3" to maximum 12". I want to know if we need to follow minimum 3" because the USB connector of the project is very close to SoC and it's around 2500mil.

               

              Best regards,

               

              Anson

                • Re: PDG routing guideline trace length question
                  Carlos_A Brown Belt

                  Hello, Ansonlin :

                   

                  Thanks for your clarification.

                   

                  Reviewing the cited information we found that this information is related to a 6-layer design, where just the first one should be 500 mils.

                   

                  It is important to let you know that the information stated in the documentation guarantees the proper functionality of the Intel devices associated with them. However, in case that you want to implement something out of the suggestions stated in the documentation, it should be tested and validated on your own.

                   

                  We hope that this information may help you.

                   

                  Best regards,

                  Carlos_A.