1 Reply Latest reply on Sep 12, 2017 8:23 AM by Carlos_A

    Unable to assign pins, DDR3, unable to build project, MAX10M50

    moverlin Community Member

      Hello all.  I am trying to use the DDR3 memory on the MAX10 FPGA 10M50 Evaluation Kit.  In Qsys, I add the DDR3 memory controller.  After I "generate HDL" in QSYS, I am told to run a tcl script so that the pins on the FPGA can be assigned to connect with the DDR3 memory on the board.  When I try to run this tcl script in Quartus, I receive the following error messages (red text) in the tcl console.

      Also, when I try to compile my FPGA design, I see the following outputs in the messages window:

       

      I am prepared to provide any other information about the project should it be needed.  I believe I have correctly added the QSYS component.

      I have generated the HDL in QSYS without any error messages (4 warnings).

       

      How should I go about solving these issues?

      Do I need to provide any additional information so that I can get accurate advice on how to resolve my issues so that I can compile my Quartus project?

       

      Thanks,

      Matt