3 Replies Latest reply on Jan 8, 2018 8:27 AM by Carlos_A

    After Bifurcated 8X lane into 4X4X link speed degrades

    Davidm71 Community Member



      I have an X99 Motherboard that I modded to allow bifurcating the last 8X pcie slot into two. This particular slot shares bandwidth behind a switch that routes half the lanes to an onboard M.2 slot hosting a Samsung 950 Pro. Limitations being you loose the last pcie slot when the m.2 runs at pcie 4x mode through the cpu which is a 40 lane 6850k. However after modding the bios of my motherboard and enabling a certain register inside the IntelSetup module I could now operate the M.2 at 4X and a second Plextor Nvme pcie card off of the last Pcie slot with the use of a bifurcated 4x4x riser card. The problem i am experiencing however is when the pcie bus is bifurcated, doesnt matter if card is connected directly to slot or not, sometimes randomly my plextor upon a reboot will be at 2.5 Gt/s operation as opposed to 8 gt/s mode. Not sure what could be cause of this except I have noticed that Lspci reports that only the first equalibration phases had completed successfully in that the 2nd and 3rd had failed. Most of the time it goes away after a reboot or driver reinstall. So if anyone can help i would appreciate it,


      Thank you.

        • Re: After Bifurcated 8X lane into 4X4X link speed degrades
          Carlos_A Brown Belt

          Hello, Davidm71:


          Thank you for contacting Intel Embedded Community.


          In order to be on the same page, could you please tell us if the affected design has been designed by you or a third-party company? In case that it is a third -party design, could you please give us all the information related to it?


          We really appreciate your help to solve this inconvenience.


          Best regards,


            • Re: After Bifurcated 8X lane into 4X4X link speed degrades
              Davidm71 Community Member

              Hi Carlos,


              Thank you for responding to my inquiry. First of all I apologize if I have posted to the wrong subsection of the Intel forums. If that is the case may the moderator place this thread in the appropriate place.


              Ok. Heres the issue.  Basically I own a Msi X99a motherboard and a 6850k processor. I figured out how to 'mod' the bios to set an address variable inside the Platform IntelRcSetup module to enable the 8X port to bifurcate into two 4X ports. This was done by changing a hex value at a certain address that corresponded to the first IIO controller.


              In anycase afterwards i noticed that my plextor M8pey drive that was inserted in the last pcie 8x slot (which shares bandwidth with the onboard M.2 controller hosting a Samsung 950 pro) would randomly upon a reboot not link up at 8 gt/s operation and at 2.5 instead. So I researched what could cause this and am exploring solutions such as setting the motherboards 'training latency timeout' timer from 1000 to 10000. Also turning on 'Extended Sync' mode on the IO controller for those ports and correcting mismatching L1 exit latency values.


              To acomplish this i'm using the RU utility to change these system register values. Not sure if its fixed as of yet though because this very random. In anycase for the most part Im able to operate two nvme drives off of the cpu pcie lanes where it was not meant to be by design but since i have a 40 lane cpu i didnt want the extra lanes go to waste. Should also mention using a Supermicro bifurcated 8x to 4x4x adapter to get at the last 4 unused lanes but this speed issue occurs with or with out the adapter.


              So my best guess as whats going on is that the bus is very noisy with all the peripherals including two video cards at 16X. Since I'm not a bios engineer familiar with pcie tech was wondering if someone with more technical experience could make suggestions?


              Thank you