Referring to the Intel document 566757, page 64, a PCB routing example is shown where the pins A2 and B1 are intended to route to test points for NCTF test functionality.
The document does not clearly state if A2 and B1 are shorted or connected on the die package to VSS(A2) or VCC(B1) respectively .
On CRB, 571483, they are obviously connected to VSS(A2) and VCC(B1) externally (what would be tricky if they were shorted on die package).
How is the electrical relationship between A2/B1, A48/B48, BG48/BF49, BG2/BF1, VCC and VSS for Cannon Lake PCH-H?
Could you also confirm that the Coffe Lake H CPUs Corner pins C1/B1, C38/B38, BR38/BT36 and BR2/BP1 are shorted together on die package and do not have any electrical potential?
Thank you for your help.
Best regards, Walt