4 Replies Latest reply on Apr 5, 2018 11:03 AM by rdebacker

    X540 SPD Pins

    rdebacker Green Belt

      I am using the X540-BT2 Ethernet controller in my design and I have a question regarding the SDP (software defined pins) pins.

      The X540 reference schematic does not tie these pins high or low.

      The X540 datasheet pin interface does not state that these pins have internal pull-ups or pull-downs.  There is a Note 1 that states these pins should have external Pup/Pdn's.

      In section 4.4.3 of the datasheet there is a statement that SDP0_1 and SDP1_1 have weak internal pull-down resistors.

      The I350 schematic checklist states that the if the SDP pins are not used they can be left disconnected.

       

      Do the SDP pins need to be connected to external pull-ups or pull-downs?

      The SDP Control Register (Datasheet 6.4.6.4) in the NVM is configured as 0x0000 for LAN0 and 0x0400 for LAN1.  Generic software controlled I/O.  All SDP pins inputs except SDP1_2.

       

       

       

        • Re: X540 SPD Pins
          Carlos_A Brown Belt

          Hello, rdebacker:

           

          Thank you for contacting Intel Embedded Community.

           

          In order to be on the same page, could you please confirm us if your consultation is related to a technical problem? In case that your answer is positive, could you please give us a detailed description of the issue.

           

          Waiting for your reply to our requests.

           

          Best regards,

          Carlos_A.

          • Re: X540 SPD Pins
            rdebacker Green Belt

            Carlos,

            No the design has not been reviewed.

            We use Altium which is not supported by Intel’s automated review process.

             

            Like I previously stated, the reference design for the X540 does not specifically state what to do with these pins.

            The datasheet contradicts itself in various sections.

             

            I do not use these pins.  These pins are floating in my current design.  What does Intel recommend?

             

            Thanks

            Rene