Hello, EKS :
Thank you for contacting Intel Embedded Community.
In order to be on the same page, could you please tell us why you really need to know if the MDIO/MDC should be managed to perform the cited conversion? Also, could you please clarify why you want a tool to program SPI file via SMBUS or MDIO/MDC? By the way, could you please let us know if you design has been reviewed by Intel?
Waiting for your reply to the previous questions.
Below are the answers to your questions
"In order to be on the same page, could you please tell us why you really need to know if the MDIO/MDC should be managed to perform the cited conversion? "
Based on the datasheet of X557 10GB KR should be the default mode. So not very sure if we need to program any registers via MDIO/MDC to have the link up and running and hence the question.
"Also, could you please clarify why you want a tool to program SPI file via SMBUS or MDIO/MDC?"
Just wondering if you guys have any upload tools like you guys have EEUPDATE for I210 programming. I210 does it via PCIe bus I gather but in this case Debug SMBUS or MDIO/MDC interfaces are available.
"By the way, could you please let us know if you design has been reviewed by Intel?"
Not yet, we are still in concept stage of the design.
Hello, EKS :
Thanks for your clarification.
Our Upper Technical Level told us that besides SerDes, MDIO/MDC and dedicated interrupt(s) are all necessary signals for X557 to operate properly. Without MDIO, any of the approved MAC controllers will be unable to manage the PHY, including reading/writing the X557 NVM to the flash. That means Intel Software Tools (LANconf, EEupdate, etc.) are incapable to program the X557 flash, instead you need the flash pre-programmed with the NVM or using a DediProg to do it.
The dual port X557 NVM in Broadwell-DE [BDX-DE V2 and Y0 Stepping] 10G LAN Enabling Kit [LEK] document number 561475 potentially could work on X557-AT (single port device SKU) because it is for the X557-AT2 (dual port device SKU), given if you have all of the necessary signals routed, so you are free to test it out. By the way, they can point you to the proper collaterals and you can see about engineering a solution and validate your design on your own because none of the approved Intel platforms for this PHY uses X557-AT.
This LEK is accessible when you are logged into your Resource & Design Center (RDC) privileged account. It can be requested by filling out the RDC Account Support form.
We hope that this information may help you.
We have a similar design with EKS.
- We have designed 3U-VPX processor which is based on Broadwell-DE board and 3U-VPX Ethernet board which is based on X557-AT2.
- We are using BDXDE_10GBASET_NO_MNG_1.13v02_800006B7.bin for Broadwell DE.
- We are using 2.B.9.A_VER380_021_BDX_X557_AT2_B1_310816.bin for X557-AT2.
- Operating system which we use on the Broadwell-DE is Windows 10.
- We are using as a driver Intel® Ethernet Adapter Complete Driver Pack, v23.2
- We connected only KR interface of CPU and X557-AT2 on main board since our MDIO and interrupt pins of CPU are not routed to the VPX connector.
- We try to all our prototype boards (5 of 5) and we cannot see the Ethernet connection.
- So our questions are;
- Is 10Gbit Ethernet connection possible to without interrupt and MDIO signals?
- Are version of NVM image which we are using latest?
Visio-Xeon_D_X557AT2.pdf 365.7 K