Hello Wired Ethernet Intel Community,
I have use INTEL I210,But I have some confused. Because INTEL I210 (layout check list ) mention that for highly dense platforms PCIe design would be to have coupling capacitors in a staggered formation but,in some INTEL document and non-INTEL document mention that differential coupling capacitors in a staggered formation prohibited. Which is Right? thanks
You answered the question yourself.
In normal conditions the coupling capacitors should not be staggered.
The exception being in a highly dense platform you may stagger the capacitors to save space but this is not ideal and this implementation should be thouroughly checked to ensure
the PCIe rules are not contravened.