9 Replies Latest reply on Aug 20, 2018 8:53 AM by twmemphis

    Upgrading Apollo Lake to 16GB DDR3L memory -40 to 95°C with DRAM from Intelligent Memory

    twmemphis Community Member

      Intels Apollo Lake CPUs can take up to 16GB DDR3L RAM at 1866MT/s speed in Non-ECC operation.

      Optionally ECC can be used with reduced maximum operation speed of 1600MT/s.

       

      These 16GB need to be split into two ranks of 8GB each. This means that each rank must be made of 8 Gigabit DDR3L components in a x8 organization.

      The manufacturer Micron had the 8Gb MT41K1G8SN devices before, but these are now EOL.  Industrial Temp or DDR3L-1866 versions were rarely or not available anyway.

       

      A good option is to use the 8Gb DDR3L Intelligent Memory DRAM-components with part# IM8G08D3FCBG (Click the part# for direct link to the datasheet!)

      These parts are available with up to DDR3L-1866 speed and also industrial temperature.

      We have already tested them successfully on multiple boards with Apollo Lake CPUs as well as others like Broadwell, Baytrail, etc!

       

      For customers having a SO-DIMM slot on their Apollo Lake boards, Intelligent Memory also offers 16GB modules with and without ECC.

      16GB Non-ECC SO-DIMM Module Part# IMM2G64D3LSOD8AG (Click the part# for direct link to the datasheet!)

      16GB Non-ECC SO-DIMM Module Part# IMM2G72D3LSOD8AG (Click the part# for direct link to the datasheet!)

       

      A list of distributors can be found here: Where to buy | Intelligent Memory

        • Re: Upgrading Apollo Lake to 16GB DDR3L memory -40 to 95°C with DRAM from Intelligent Memory
          FrankWeerdenbur Green Belt

          Hello Memphis,

           

          Thank you for sharing this information, because with the now good long life support of Intel processor you do not want other devices on the board to go end-of-life.

           

          A remark on actually using the memory above +85°C, see your datasheet:

           

          Refresh cycles:

          - Average refresh period

          1. 7.8 µs at 0°C ≤ Tc ≤ +85°C
          2. 3.9 µs at +85°C < Tc ≤ +95°C

           

          So for this the BIOS needs to be customized to set the memory refresh period to 3.9 µs.

           

          Good you have also implemented this feature in the SPD EEPROM on the memory module. In this case the (customized) BIOS can set the refresh period corresponding the bit in the EEPROM.

           

          Best regards,

          Frank van Weerdenburg

          ELTAN BV

            • Re: Upgrading Apollo Lake to 16GB DDR3L memory -40 to 95°C with DRAM from Intelligent Memory
              twmemphis Community Member

              You are perfectly right.

              With an SPD Eeprom having an integrated Temperature Sensor you can set the system (via SPD settings) in a way that it adjusts the refresh rate on its own depending on the actual temperature. Also you can activate ASR mode in the SPD which takes automatic care of the refresh rate in self-refresh mode.
              Or alternatively you could permanently set the refresh rate to 3.9µs, which costs a bit of performance (not too much though)

               

              The DDR3 JEDEC standard states that the refresh rate needs to be doubled when the tCase (temperature on DRAM-surface) exceeds 85°C. The same rule also applies for other memory technologies such as DDR2 or DDR4 or LPDDR4.

              Reason: Operating at high temperature reduces the data-retention time of the memory-cells due to higher leakage, which can lead to random & transient single bit errors. To work against this, doubling the refresh rate is very effective.

               

              Bit-flips in memory can also occur due to numerous other reasons (radiation, intensive operating, VRT effects), while high temperature surely is the most critical.

              An addition method to make systems highly reliable / to reduce the frequence "single event upsets" is to use ECC error-correction on the memory. This requires the memory bit-width to be expanded from 64 to 72 bits to store the additional parity data for ECC, so you need more components.

              Intelligent Memory also has DRAM with "on chip ECC", which means the ECC is executed by the DRAM, thus the CPU does not need to be ECC capable. But such ECC DRAMs are only available from IM in small capacity like 1 Gigabit (DDR1, DDR2, DDR3).

              New DDR4 8Gb with ECC and also LPDDR4 4Gb+8Gb with integrated ECC are planned to be released by Intelligent Memory later this year or next year.

              Regards,

              Thorsten

              • Re: Upgrading Apollo Lake to 16GB DDR3L memory -40 to 95°C with DRAM from Intelligent Memory
                twmemphis Community Member

                I have a question:

                I see some boards with Apollo Lake having two SO-DIMM sockets.

                As the 8 Gigabit DDR3L components are working well, a Dual-Rank SO-DIMM can have 16 Gigabyte.

                Has anybody ever tested if the Apollo Lake can be expanded to 32GB by using 2 pieces of 16GB modules?

                Unfortunately I have no board with two SO-DIMM sockets on hand. But if anybody here in the forum would like to try, we can send samples to test.

                Regards,

                Thorsten

              • Re: Upgrading Apollo Lake to 16GB DDR3L memory -40 to 95°C with DRAM from Intelligent Memory
                Carlos_A Brown Belt

                Hello, twmemphis:

                 

                Thank for contacting Intel Embedded Community.

                 

                In order to be on the same page, could you please let us know the part numbers and SKUs related to this situation? By the way, could you tell us if the affected is a third-party design or it has been developed by you? In case that it is a third-party device, could you please give us all the information related to it?

                 

                Wating for your reply.

                 

                Best regards,

                Carlos_A.