5 Replies Latest reply on Sep 21, 2018 12:25 PM by Carlos_A

    Debug version of FSP2.0 for Skylake

    christiangmeiner Community Member

      Hi.

       

      I am currently working on a coreboot/U-Boot based custom boot solution. At the moment the used COM express board works most of the time. If it fails it looks like there are some global resets triggered by the FSP followed by wired pcie resets which can result in a total hang or in boot times more then one minute.

       

      Some coreboot guys told me that I should try to get access to a debug version of the FSP. I really need to get this working asap and the next Apollo Lake based design is waiting for me (if the FSP/coreboot/U-Boot plan works).

       

      I think my employer should have the nessesary NDA with Intel.