11 Replies Latest reply on Nov 15, 2018 3:36 PM by VGH

    i210 PCIe bus detection , flash read

    VGH Green Belt

      I have an embedded i210 design (copper Ethernet connection). The i210 controller is connected to a Com Express i5-7300U module.  The basic design boots and can load the Ubuntu OS. Doing an lspci scan I see no indication the i210 is on the bus. The PCIe bus works OK, I’ve tested a MiniPCIe NIC (i210 version) and operates OK.  I’ve changed the NVM_SI (pin 12) signal to a 10K pull-down.  The Flash-EEPROM (SST25VF040B-50-4I-SAE) is new (blank).  I’ve check DEV_OFF_N signal and it’s connect to a 3.3K pull-up.  SDP1 (pin 61) is open.  I have a 25MHhz oscillator connected to XTAL1 (pin 46). XTAL2 (pin 45) is open.  LAN_PWR_GOOD (pin 1) is connected to 3.3K pull-up.  I checked power and the part is wired per the datasheet.

      My understanding is the Flash should reload on a PCIe reset (figure 4-2 datasheet). I’m not seeing any activity on the NVM_SI (pin 12). 

      At this point it’s unclear why I’m not seeing the device on the PCIe bus; even if the OS didn’t load the drivers. I’ve seen the same issue on 4 boards now. Also, PREBOOT and EEPROM Access tools don’t see the i210 ether.

      Any idea on what could be holding off the PCIe connection and/or the flash read?

        • Re: i210 PCIe bus detection , flash read
          Carlos_A Brown Belt

          Hello, VGH:

           

          Thank you for contacting Intel Embedded Community.

           

          We suggest you verify that the affected design fulfills with the guidelines stated in the answers to the questions 2.23, 2.9, 2.16, 2.28, 2.31, and 2.35; on pages 9, 6, 8, 10, and 11 of the Intel(R) Ethernet Controller I210/I211 Frequently Asked Questions (FAQs) document # 334026.

           

          We hope that this information may help you.

           

          Best regards,

          Carlos_A.

            • Re: i210 PCIe bus detection , flash read
              VGH Green Belt

              Hi,

               

              FAQ 2.23: I have a 1K PD and 33.3K PU on pin-12

               

              FAQ 2.9: I started with a blank part but replaced with a pre-program part later. In both cases I didn’t see any active on the NVM_SI pin

               

              FAQ 2.16:  I used “Dev_Start_I210_Copper_NOMNG_4Mb_A2_3.25_0.03.bin” for the pre-program part (Microchip PN SST25VF040B-50-4I-SAE)

               

              FAQ 2.28: I used 85-Ohms for the PCIe. The bus is short, 2.8” for PCIe-RX and 3.4” PCIe-TX

               

              FAQ 2.31:  The SMB bus is connected to 10K PU

               

              FAQ 2.35:  not using Spread Spectrum Clocking

               

              I’m not see any active on the NVM_SI pin on power-up or PCIe reset. I have both the 25Mhz clock and PCIe clock functioning. The basic PCIe bus is work; I can use and off-the-shelf i210 NIC the Mini-PCIe slot and get full operation. The Mini PCIe slot is connected to PCIe port 1 and the embedded i210 is connecter to port 0.  Is there a way to verify the i210 is internally operating.

               

              Thank you,

                • Re: i210 PCIe bus detection , flash read
                  Carlos_A Brown Belt

                  Hello, VGH:

                   

                  Thanks for your clarification.

                   

                  Based on your previous communication, could you please let us know the sources that you have used to implement  the affected design? By the way, could you please let us know if its schematics and layout has been reviewed by Intel?

                   

                  We really appreciate your cooperation.

                   

                  Best regards,

                  Carlos_A.

                    • Re: i210 PCIe bus detection , flash read
                      VGH Green Belt

                      No, the schematic and layout haven’t been reviewed by Intel. Please let me know how to submit the design files.

                        • Re: i210 PCIe bus detection , flash read
                          Carlos_A Brown Belt

                          Hello, VGH:

                           

                          Thanks for your reply.

                           

                          You may find all the details related to the schematics and layout review service at the Design Review Services website.

                           

                          We hope that this information may help you.

                           

                          Best regards,

                          Carlos_A.

                            • Re: i210 PCIe bus detection , flash read
                              VGH Green Belt

                               

                              Hi, the schematic/layout review is limited. They don’t support Altium Designer. At this point I’m trying to understand if I have design issue or a manufacturing deficit. I see power and clocks to the i210 device. But don’t see any active on the NVM_SI (pin 12) at power-up or PCIe_reset. DEV_OFF_N (pin 28) / LAD_PWR_GOOD (1) are on PU to 3.3V and SPD1 (PCIe_DIS, pin 61) in open. I have a 1K PD on NVM_SI to disable the Security_En function. Are there any other strappings that would disable Flash read?

                               

                                • Re: i210 PCIe bus detection , flash read
                                  Carlos_A Brown Belt

                                  Hello, VGH:

                                   

                                  Thanks for your reply.

                                   

                                  In order to help you, as a reference please review the following web site:

                                   

                                  Export to AutoCAD (PCB) | Online Documentation for Altium Products

                                   

                                  We hope that this information may help you.

                                   

                                  Best regards,

                                  Carlos_A.

                                    • Re: i210 PCIe bus detection , flash read
                                      VGH Green Belt

                                      Hi, I’m working on getting a DXF version. We’re in the process of verifying the export is correct.

                                       

                                      Van

                                        • Re: i210 PCIe bus detection , flash read
                                          VGH Green Belt

                                          Hi, still not see any life in the i210 part. I’m working on getting a new part and replacing. I’ve checked the schematic and layout serval time. X-Ray the part to ensure solder connection.  I’m thinking the parts may be some odd security mode, see datasheet:

                                           

                                          3.3.1.2 Flash Detection, NVM Validity Field, and Non-Secure Mode

                                           

                                          In cases of an invalid NVM Validity field contents, or no Flash detection, auto-load from Flash by

                                          hardware or firmware after power-up or reset is not performed.

                                           

                                          Do you know of any strapping or setting to override?

                                           

                                          Van

                                            • Re: i210 PCIe bus detection , flash read
                                              Carlos_A Brown Belt

                                              Hello, VGH:

                                               

                                              Thanks for your update.

                                               

                                              Even without a flash part the i210 should still come up on the PCI bus as ID 1531. In case that it is undetected on the PCI bus at all, it has nothing to do with the flash part you are using.

                                               

                                              We suggest you if it is possible, probe the PCI lines with an analyzer to see if the i210 is reporting back at all, If not, then the basic schematic and layout need to be gone over again.

                                               

                                              We hope that this information may help.

                                               

                                              Best regards,

                                              Carlos_A.

                                                • Re: i210 PCIe bus detection , flash read
                                                  VGH Green Belt

                                                  Sorry for taking so long to get back,

                                                   

                                                   

                                                   

                                                  I’m still having issue with the i210 enumerating in Linux or EFI shell . I fixed a couple of issue that was keeping the Flash EEPROM on the i210 from configuring.

                                                   

                                                   

                                                   

                                                  What as fixed

                                                   

                                                  3.3V Clock oscillator was running at wrong voltage level (i210 needs something like 1.5V to 2.0V). switch to a crystal oscillator

                                                   

                                                  Add 1K PD on NVM_SI pin 12; this disable the Flash EEPROM security so it can be accessed.

                                                   

                                                  Remove wake-on LAN connection, pin 16

                                                   

                                                  Remove NC_SI_ARB_IN PU, this was in the Intel schematic check-lest

                                                   

                                                  Replaced Blank Flash EE with known working one (using Winbond W25Q16JVSNIQ ) from a i210 NIC.

                                                   

                                                  Added series 22.1-Ohm resistor the NVM_SI (pin-12) to Flash EE. This was to improve signaling SI.

                                                   

                                                   

                                                   

                                                  What is known

                                                   

                                                  Seeing 25MHz clock at XTAL1 (pin 46)

                                                   

                                                  Seeing Flash EE activity on power-up and PCIe hardware reset

                                                   

                                                  Seeing PCIe port 1 00:1C:00 in EFI and Linux. The i210 is connect to port 1

                                                   

                                                  Seeing PCIe clock at chip

                                                   

                                                  i210 not seen by the Intel EE access tool

                                                   

                                                  Add-in i210 NIC on mini-PCIe slot (connected to port 2) is operational. Seen by OS and EE access tool

                                                   

                                                  Activity LEDs are on when Ethernet cable is connected

                                                   

                                                   

                                                   

                                                  Check layout and board

                                                   

                                                  SDP1 [PCIe_DIS] pin 61 open, all other SDP pin open

                                                   

                                                  DEV_OFF_N pin 28 PU to 3.3V

                                                   

                                                  LAN_PWR_GOOD pin 1 PU to 3.3V

                                                   

                                                  Flash EE power from same 3.3V power rail as i210

                                                   

                                                  Seeing 1.5V and 0.9V from i210

                                                   

                                                  SMB signal unused,  10K PU

                                                   

                                                  JTAG signal unused, 10K PU

                                                   

                                                  NC_SI signal unused, 10k PU/PD as indicated in schematic check-list and reference design

                                                   

                                                  Pin 21/20 i210 Tx connect  to 10nF 16V AC caps (dielectric X7R) AC cap connected to ComEx Pin B68/B69

                                                   

                                                  Pin  24/23 i210 Rx connect to ComEx Pin A68/A69

                                                   

                                                   

                                                   

                                                  Configuration

                                                   

                                                  Com Express KL-i5

                                                   

                                                  OS Ubuntu 18.04

                                                   

                                                   

                                                   

                                                  Any ideas would be helpful

                                                   

                                                  Thank you,