The key question here is: On an i5 520M chipset is it possible to alter a i5 register to make the i5 send back read-data payloads of 128byte rather than the PCIe default 64byte payloads.
Here's the rationale:
I have a i5 520M chipset system that uses a custom PCI-express card plugged into the 16lane connector. Our PCie card attempts to Issue DMA read requests to the i5 root and extract data from the system memory at maxmimum theoretical read rate. The PCIe card issues 128byte 3DW reads at maximum data rate to the i5. However, the i5 chipset returns the data in 64byte payloads rather than the 128byte.
The key issue here is that by slicing the packets up the maximum effective bandwidth of the PCIe link is now compromised and reduces by an enormous amount. The overhead of two-(3DW Headers.DLLP-Acks and Update-FC's cripple the performance of this port)
As a comparision, If i use a i5 desktop chipset then it returns the 128byte payload packets as the requester sets
I appreciate the 64byte payloads from the root are all covered in the PCIe specification etc... but can we tell the i5 520M to NOT do this?
Thanks to all