Intel's expert on this subject pass along the following:
The preferred method for physical layer 1Gbase-T clock testing is performed is using IEEE test mode 2 or 3 (TM2 Mstr, TM3 Slv)
TM2 and TM3 put a 125GHz replica of the GMII clock on the (four) MDI pairs.
The test mode is Mandated by IEEE for 126.96.36.199.5 Transmitter timing jitter test.
It can be used for 188.8.131.52.6 Transmit clock frequency test and is an effective clock measurement configuration.
Transmitter test mode operations are defined by bits in phy register 9.15:13.
Test mode 2—Transmit jitter test in MASTER mode
Bit 1 (9.15) =0
Bit 2 (9.14) =1
Bit 3 (9.13) =0
I hope this helps
J. Felix McNulty
Community Moderator (Intel contractor)
Hello Felix, Thank you for your help. But I want to use the test ports also for the jitter measurement. I know there’s a work around, but we are developing a test solution for the IEEE Compliance test. So we need to be able to do the jitter tests on both ways. So I need to activate the test port anyway. Greetings Philipp
Hello again Philipp:
Here is some more info from the Intel team. Please note Gordon's comment at the bottom of the message about the upcoming discontinuance of the 82541P1 part. If you are developing a new product you might want to consider looking at a newer controller ?
Thanks for the interest in enabling the test port for jitter measurement.
I have found some Phy settings that are relevant to the request for work around for enabling test port (Pins B14 & D14, IEEE TEST +/-).
I have not tested the following sequence so this information is provided without additional support or implied usability.
Jitter Test Clock
When high, it sends Jitter Test Clock out
This bit works in conjunction of internal PHY register bit 0x4011.15. In order to have the clock probed out, it is required to perform the following write sequence:
PHY REG 18.5 = 1
PHY REG 31 = 0x4010 ( page select)
PHY REG 17 = 0x0080
PHY REG 31 = 0x0000 ( page select)
Our recommendation is to use a simplified MDI clock Jtclk measurement using TM2 for jitter testing as previously described.
Some Legacy controllers had the GMII interface exposed externally including the Tx-TClk test port.
This was useful during validation of Intel MAC to external Phy connections using GMII interface.
The GMII interface and TX_TCLK is not found externally available on recent Intel Gigabit Ethernet controllers.
Tx_Tclk is an internal clock that is used to drive phy signals, it is by design a low jitter clock.
When designers take the internal clock and try and replicate it externally there is the additional cost
and complexity associated with adding a low jitter driver for the test clock. Bringing this clock out
to the ball or lead of a package can also change the characteristic of the original clock as well as the
externally measured clock may have phase shift across clock domains that causes complications in jitter testing.
UNH (www.unh.edu) operates an independent interoperability test facility at its Gigabit Ethernet Consortium and allows for test cases where there is no Tx_TCLK access.
Using Test Mode 2 to measure Transmitter clock jitter on the MDI is an effective verification of clock health for production interoperability testing.
The question mentions work in progress to develop a test solution, it should be noted that the 82541PI referenced and related family is near EOL.