In power sequencing document "Crystal Forest Power Sequencing and Reset Timing Requirements", on Figure 2, there is power sequencing requirement on power rails where all power wells are treated individually. On figure 3 it is mentioned that all rails can be powered on simultaneously. What is difference between these two?
"During normal operation, the power sequence is SUS -> AUX -> MAIN. Main power can only operate when all the power rails come up. In the case without SUS Supply Well design, SUS rails can be sourced from MAIN Supply Well if desired. AUX rails can be also sourced from MAIN Supply Well if desired. All Supply Wells can be power on simultaneously."
what is the case without SUS supply well design? can somebody give example?
"Power on the lowest voltage rail from the on board power supply first (recommended), or power on all onboard supplies simultaneously. Otherwise, the ‘power-good’ gating signal should be unasserted when the low voltage supply is off."
by unasserting power-good can we violate sequencing and then assert power-good?
"The AUX well is typically tied to the SUS well if Wake On Lan (WOL) functionality is used or if the MAIN rail has no WOL".
what is meaning of this statement?