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Here is a response from Intel’s BLDK expert:
All post code are only used in MRC code as follows:
/* Checkpoint progress indicators written to port 80h */
#define STS_CHIPSET_INIT 0xA0 // Initialize processor and version number saved
#define STS_RESET_STATE 0xA1 // Detect host reset state
#define STS_FREQ_DETECT 0xA2 // Detect DDR frequency
#define STS_PARAM_CONFG 0xA3 // Detect DDR parameters
#define STS_VERIFY_CONFIG 0xA4 // Verify DDR parameters programmed
#define STS_JEDEC_INIT 0xA8 // Perform the appropriate JEDEC initialization
#define STS_CPU_CONFIG 0xA9 // Clear FIFO command sent to P-Unit
#define STS_MRC_DONE 0xB6 // End of memory initialization
From the information you provided, “0xB6” means the system probably passed the MRC initialization successfully.
I hope this helps
J. Felix McNulty
Community Moderator (Intel contractor)
Thank you for that. I grepped for those #define's in my BLDK source and was not able to find them so I assume they are in some non-open part of the BLDK code base?
We'd really like to get this board doing something other than sending POST codes soon. Preferably outputing the UEFI shell over the serial console (this board is headless). We're willing to pay for some help from a contractor if thats what it takes. As it is right now, we have no idea where to even start looking for potential problems with our prototype with only undocumented POST codes to go by.
Is the 0xD2 POST code we get before the 0xB6 any clue? What is the next POST code that would be sent after 0xB6 (our last one before lockup) since it seems the POST codes on the BLDK are not an indication of errors but indications of boot status.
My email address: email@example.com
The code 0xB6 is the last code that is outputted by the default bootloader, but it is far from finished at that moment (only the memory initialization has finished). What you can do is download the BLDK source package (CB-EDKII-PostGold-18.104.22.168) and add postcodes yourself to see the progress of the bootloader.
My apologies for coming back to this old thread but I could not find any help elsewhere (even from Intel Support).
I am FAE and a customer of mine is running a very seemed problem now.
The difference is that they are NOT using BLDK, but Coreboot (that is using FSP, by its turn).
Sequence codes are the same:
- A2, A3, A4, A8, D2, A9, B6
Generated Coreboot firmware hangs after "B6".
Intel FSP for Queens Bay running on Atom processor E620 hangs and I cannot find any documentation on the meaning of the displayed status codes.
Where is can I find the meaning of this codes for sure?
Since FSP only gives me a binary to link against my firmware (Coreboot), does anyone have any clues on how to check if things are running fine in the FSP part?
The B6 code means that the MRC has completed successfully.
The Intel® Firmware Support Package is available here. Look for "Intel® Atom™ processor E6xx series with Intel® Platform Controller Hub EG20T (formerly Queens Bay: Tunnel Creek and Topcliff)"
If your customer has an issue, you may want to submit an issue for them via IPS.
The B6 code is referenced on page 35 in the "Implementing Network Booting Using Intel® BLDK" white paper".
"The 7-Segment LED display should read b6. If it reads 00 or any other value then the image is probably corrupt and malfunctioning."