1 Reply Latest reply on Aug 30, 2013 2:00 PM by LynnZ

    Running IPP in AVX2 mode on 4th-generation Intel Core i7 processors

    Green Belt

      I am currently using a (purportedly) Core i7-4700EQ Mobile processor (comprised by a SOM-5894 COM-Express board from Advantech). It is possible that I am using an engineering sample processor since its type is reported as "0000" by the BIOS.

       

      My application uses IPP (7.1). Specifically, I am trying to use the library in AVX2 mode. I am using static linkage (#include <ipp_h9.h> before #incluie <ipp.h>). My code runs in 32-bit mode.

       

      It turns out that a call to ippsFFTInitAlloc_C_32fc crashes upon hitting on an SHLX opcode belonging to the BMI2 instruction set extension.

       

      I was originally under the impression that BMI2 is part of the 4th generation (a.k.a. Haswell) architecture, however the particular that I am using reports that it does not support BMI2 (nor BMI1).

       

      I have the following questions:

       

      1. Are there other 4th generation Core i7 processors that do support these instructions?

      2. Does IPP specifically mandate support of BMI2 (in addition to support of AVX2) when trying to use it in AVX2 mode?

      Thanks,

       

      Beni Falk

        • Re: Running IPP in AVX2 mode on 4th-generation Intel Core i7 processors
          LynnZ Brown Belt

          Beni,

          You indicated that a pre-release HSW CPU was used; is AVX2 enabled for the processor?

          I'm not sure how AVX will behave on pre-launch HSW CPU; use CPUID to check if AVX2 is enabled.

          Hardware support for AVX2 is indicated by CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]=1.

          Also refer to this guide for more info:

          http://download-software.intel.com/sites/default/files/m/8/a/1/8/4/36945-319433-011.pdf

           

          Here’s the routine to do so:

           

          INT supports_avx2()

          { ; result in eax

          mov eax, 1

          cpuid

          and ecx, 018000000H

          cmp ecx, 018000000H; check both OSXSAVE and AVX feature flags

          jne not_supported

          ; processor supports AVX instructions and XGETBV is enabled by OS

          mov eax, 7

          mov ecx, 0

          cpuid

          and ebx, 20H

          cmp ebx, 20H; check AVX2 feature flags

          jne not_supported

          mov ecx, 0; specify 0 for XFEATURE_ENABLED_MASK register

          XGETBV; result in EDX:EAX

          and eax, 06H

          cmp eax, 06H; check OS has enabled both XMM and YMM state support

          jne not_supported

          mov eax, 1

          jmp done

          NOT_SUPPORTED:

          mov eax, 0

          done:

          }