20 Replies Latest reply on Apr 22, 2016 11:58 AM by Carlos_A

    I2S from SDIO with a clock rate of 49.152 MHz master clock rate?

    sin Green Belt

      Dear experts,

       

      I wouild like to interface an I2S type 24-bit DAC, Texas Instruments (Burr-Brown) PCM1792A to the Galileo board.

      As I need the SCK rate of 49.152 MHz it seems to me that the only serial type port for my application is the SDIO

      interface. In addition to the SCK = SDIO CLK I need the three I2S signals as follows:

       

      ADATA = SDIO DAT0

      BCK    = SDIO DAT1, 192000 x 24 = 4.608 MHz

      RLCK  = SDIO DAT2, 192 kHz

       

      Is this the way to go or do you have better ideas.

      I want to keep the components count at the minimum and I would like to use the DMA trsansfer.

      The device driver should manipulate the DAT1 and DAT2 in such a way thet the properly timed

      BCL and RLCK are generated.

       

      Please comment and advice!

        • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
          LynnZ Brown Belt

          Hello.  Thanks for visiting the Embedded Community.  We'll get back with you shortly with a response.  LynnZ.

          • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
            chaas Green Belt

            Hello Sin,

             

            There is no provision for I2S on the Galileo. In addition, we do not have data for re-purposing SDIO for the hardware interface you've specified.

             

            Best Regards,

            Casey H.

              • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
                sin Green Belt

                Hello Casey,

                 

                I know that there is no provision for I2S on the Quark processor.

                But I need one and therefore I would like to use the SDIO port to emulate I2S as

                I sketched in the original mail.

                 

                My first subproblem is to generate the 49.152 MHz SCK for my PCM1792A audio DAC.

                Can I get this clock out from the Quark chip by scaling the internal clocks on the chip?

                The best that I could figure out so far is to replace the 25 MHz processor crystal by a

                24.576 MHz crystal and then the SDIO SCK would be just right for me. Would this

                harm the PCIe operation?

                 

                The actulal I2S signals ADATA, RLCK and BCK I am planning to implement

                using SDIO pins D0, D1, and D2. This means that I have to manipulate the

                data to those outputs so that it looks like what the I2S specification requires.

                Got the idea? I am ready to write the driver for this and there I would like to

                use the DMA to do the actual transfer from my buffer area to thew SDIO/I2S

                port. I have not yet studied the Quark clock signal generation capabilities in

                detail and neither have I calculated the driver CPU loading but it seems to

                me that the loading, especially with DMA would be reasonable.

                 

                Please comment!

                  • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
                    Brown Belt

                    Hi Sin,

                     

                     

                    o    I have carefully read this case. And I don't suggest you to replace the 25 MHz processor crystal by a 24.576 MHz crystal. The clock of the PCIe is 100MHz followed PCIe specification, so if you do that, the PCIe operation maybe does not work normally.

                     

                     

                    o    And as Casey said, the Quark processor does not provide provision for I2S, if you want to use the SDIO port to emulate I2S, we cannot guarantee the stability of the signal.

                     

                     

                    My advice to you is don't design the board at first, try to do some experiments to validate the feasibility on the Galileo board of the above two points.

                    o   And if you have access to IBL, you could refer to document ID: 516704, Chapter 8, page 108.

                    New Bitmapage.jpg

                     

                    Best regards,

                    William

                    1 of 1 people found this helpful
                      • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
                        sin Green Belt

                        Thank you for your constructive help WilliamC!

                         

                        And yes, I was planning to experiment with the Galileo board and a PCIe device

                        to see if if the lowered clocc rate is really a problem there. My only PCIe device

                        will be the Intel Centrino Advanced-N 6502. If it works properly and reliably with

                        Galileo at the 1.7 percent underclocking I will proceed to prototype with my own

                        I2S audio DAC board. I will also study if the 49.152 MHz clock could be synthsized

                        within the Quark from the 25 MHz main processor clock (which I doubt). Finally

                        I will try to operate my DAC with the 50 MHz SCK. It is used within the DAC to

                        clock the digital filters so I think the performance of the DAC may be compromized

                        if the clock is not a multiple of the data rate...

                         

                        Does anybody know a board similar to Galileo which would have both the PCIe

                        and the I2S?

                         

                  • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
                    sin Green Belt

                    Let me state my idea a little bit more clearly.

                    I would like to connect the Intel Dual Band Wireless-AC 7260 to the Galileo board with the PCIe.

                    I would like to use the Linux/Android drivers with it.

                    As my application is an embedded one I will NOT need any other PCIe clients.

                    Then I want to connect a standard I2S type DAC to the Galileo board.

                    As I need the 49.152 MHz system clock I want to replace the 25 MHz master crystal

                    on the Galileo board by the same mechanical size 24.576 MHz crystal

                    My SDIO SCLK is then just right for the DAC.

                    In addition I need the 12.288 MHz BCL bit clock and the 192 kHz RLCL

                    right-left channel clocks for my DAC.

                    For the BCL I am planning to use the (scaled) SPI clock and for the

                    output data the MOSI signal. The 192 kHz RLCK should be possible to

                    generate with a GPIO PWM pin or with a legacy timer output in the toggle mode.

                     

                    Could this possibly work?

                    And if not, why not?

                     

                    I would really want to see the Intel Dual Band Wireless-AC 7260

                    block diagram and even more the schematics!

                     

                    siñ

                      • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
                        chaas Green Belt

                        Hello again Sin,

                         

                        We are looking into your request for information on the Intel® Dual Band Wireless-AC 7260.

                         

                        With regard to your ideas on changing the crystal, this is not something we have validated, and therefore we are unable to provide additional guidance for you.  One suggestion is to try posting your question in the Maker community for assistance from others that may have experience doing the same.

                         

                        Best Regards,

                        Casey H.

                        1 of 1 people found this helpful
                          • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
                            sin Green Belt

                            Thank you for your helpful add prompt reply Casey H.,

                             

                            The Intel® Dual Band Wireless-AC 7260 information would be most welcome.

                            I mainly want to check how the clocking of the different blocks is organized to

                            see if my idea has any chance to work in practice.


                            I already found a replacement crystal from Mouser and my plan is to get

                            two Galileo boards, one as reference and the other for modifications.


                            I fully understand that working outside of the specification is my own responsibility

                            and I can accept it since I am now working with a proof-of-concept rather than

                            with a serious prototype. Quark would - in many ways - be the ideal chip for my

                            project so I am willing to do my hacking.


                            I wonder if there are Quark versions with a high speed (50 Mbit/s) synchronous

                            serial port on the Intel road maps? I have successfully used two TI McBSPs as

                            such with the I2S protocol running in one of them and the other just generating

                            the 49.152 MHz SCL.


                            I will now also contact the Maker community for additional advice,


                            Best Regards,

                            siñ




                              • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
                                stephenjin Green Belt

                                Hi Sin,

                                 

                                I am sure Casey will help providing the information for Intel® Dual Band Wireless-AC 7260,

                                The information we got so far for the next gen is not detailed enough to sepcify the speed of the UART controller, but If I am not mistaken, the next gen Quark SOC will include an I2S for audio purpose, I am not sure that is going to help.

                                 

                                Best Regards

                                Stephen

                                  • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
                                    sin Green Belt

                                    Dear Stephen,

                                     

                                    As the I2S is a synchronous serial interface I wonder how it will be related to the UART controller.

                                    For my decisions it would be really important to get an idea about when the Quark SOC with the

                                    I2S interface can be expected and what will be the maximum bit rate of it. I basically need a

                                    bit rate of 2 x 32 x 192000 = 12.288 Mbit/s. This is the rate of the I2S BCL. As the system clock

                                    should be four (or two) tines the bit rate I would also need that 49.152 MHz output from the SOC.

                              • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
                                chaas Green Belt

                                Hello Sin,

                                 

                                We've been able to confirm that neither the block diagram nor the schematics for the Intel Dual Band Wireless-AC 7260 are available for distribution.

                                 

                                Best Regards,

                                Casey H.

                              • Re: I2S from SDIO with a clock rate of 49.152 MHz master clock rate?
                                kdubious Community Member

                                Was a solution ever found to this?