4 Replies Latest reply on Nov 11, 2014 2:54 AM by BenF

    PCH EG20T: Is I2C interface capable of handling clock stretching?

    Community Member

      Hi community,


      we are using the I2C interface on the PCH EG20T to communicate with a power supervisor under on-Time RTOS32. The I2C access is EEPROM based, with 16 bit addressing. The power supervisor device needs to do some clockstretching, if its not ready to responde immediately. If clockstretching is enabled, the I2C master in EG20T generates an arbitration lost IRQ. Now my basic question is: Is I2C interface capable of handling clock stretching?


      Some details: Our driver depends on the flow description of the EG20T handbook. We also looked at the Linux driver and its equivalent. For a status read on the power supervisor device, I do the following sequence:

      1. Write device address 0x53, R/W bit clear for writing, perform I2C start condition
      2. Write high byte of register address to read from
      3. Write low byte of register address to read from
      4. Write device address 0x53, R/W bit set for reading, perform I2C restart condition
      5. Read register data which is my status byte
      6. Perfom a I2C stop condition


      For some explanation, below a screenshot. We have inserted 100 ohms resistors in the SCL (yellow)/SDA (light blue) lines, to distinguish between the drivers. If signal goes low to ground, EG20T is driving the line, if it goes only to 0,5V, the power supervisor is driving the line. The sequence on the screenshot shows the status read access upon point 4: I2C restart condition, device addressing with R/W bit set. Now you can see a short clockstretching from the slave, holding the SCL line low for shorter than 10us. Now the data read starts and should clock out 8 pulses. But while the 5th clock everything blocks, EG20T drives SDA low and after about 3ms I got an arbitration lost IRQ (the magenta peak at the trigger)


      Is this a known issue or what we are doing wrong?


      Best regards,