We've got feedback from our engineers, here is the information they provided for us, I hope you find it useful:
There are actually three UARTS on the Bay Trail SoC – two HSUARTs that are part of the Serial IO (SIO) block of devices, and one legacy UART, that is part of the Platform Controller Unit (PCU) block of devices.
The HSUART registers are accessed through PCI BARs, whereas the legacy UART uses the legacy COM1 I/O space registers, 3f8h-3ffh.
Whether or not they disable the on-chip HSUARTs is irrelevant, as they don’t use the legacy I/O space addresses for COM1 and COM2.
Although you can disable the HSUARTs with the BCT, the legacy UART cannot be enabled or disabled via the BCT. The legacy UART is actually enabled in coreboot - file coreboot/src/soc/intel/fsp_baytrail/romstage/romstage.c calls function byt_config_com1_and_enable(), which is implemented in file coreboot/src/soc/intel/fsp_baytrail/romstage/uart.c and sets the bit to enable the legacy UART (it’s disabled by default when the chip powers on). This could be replaced by code that initializes COM1 on the Fintek part instead of the UART.
Note that the FSP might also enable the legacy UART internally during the call to FspInitEntry. If so, then it would simply need to be disabled again in the continuation function, which, in coreboot, is function romstage_main_continue() located in file coreboot/src/soc/intel/fsp_baytrail/romstage/romstage.c.
Here is the public datasheet for reference on the various UARTs: