4 Replies Latest reply on Nov 18, 2014 5:31 PM by James_Lee

    [Intel FSP] Bay trail fsp how to disable internal SIO?

    James_Lee Green Belt

      Hi All,

          I working coreboot project Bayley bay, my platform is Bay trail+a Fintek SIO ,

      the code base is coreboot+ Intel baytrail FSP GOLDEN 2, I want use external SIO com1/2

      to instead Intel internal COM1/2, but no success, below is my procedure.

         1. Leaveage a SIO init code from a MP project.

         2. Use BCT to disable FSP HSUART1/2.

         3, Disable devicetree.cb intel hsuart1/2.

         3. To boot then show below message

       

        just show below message, enter to OS (DOS or WINDOWS) the COM all fail,

      I think, I progamming is correct, but FSP look like will block out the  UART IO Addreess,

      so, have anybody can tell me how to fixit?Thanks.

       

                                            BestRegards

                                                               James

        

       

      coreboot-4.0-7155-g16407ab-dirty Mon Nov 17 02:58:02 PST 2014 starting...

      RTC Init

      Starting the Intel FSP (early_init)

      PM1_STS = 0x6900 PM1_CNT = 0x0 GEN_PMCON1 = 0x1001849

      prev_sleep_state = S0

      Configure Default UPD Data

      SPD Addr1:  0xa0

      SPD Addr2:  0xa2

      Tseg Size:  8 MB

      MMIO Size:  2048 MB

      IGD Memory Size: 64 MB

      Aperture Size:  256 MB

      GTT Size:  2 MB

      MIPI/ISP:  Enabled

      Sdio:   Enabled

      Sdcard:   Enabled

      Sata:   Enabled

      SATA Mode:  AHCI

      Lpe:   Disabled

      Lpe mode:  PCI

      SIO Dma 0:  Disabled

      SIO I2C0:  Disabled

      SIO I2C1:  Disabled

      SIO I2C2:  Disabled

      SIO I2C3:  Disabled

      SIO I2C4:  Disabled

      SIO I2C5:  Disabled

      SIO I2C6:  Disabled

      Azalia:   Enabled

      SIO Dma1:  Disabled

      Pwm0   Disabled

      Pwm1:   Disabled

      Hsuart0:  Disabled

      Hsuart1:  Disabled

      Spi:   Enabled

      eMMC 4.1:  Disabled

      eMMC 4.5:  Enabled

      Xhci:   Disabled


        • Re: [Intel FSP] Bay trail fsp how to disable internal SIO?
          AdolfoS Brown Belt

          Hello James_Lee

           

          We are investigating your issue, and will reply back as soon as possible with useful information.

           

          Best Regards,

          Adolfo

          • Re: [Intel FSP] Bay trail fsp how to disable internal SIO?
            AdolfoS Brown Belt

            Hello James_Lee

             

            We've got feedback from our engineers, here is the information they provided for us, I hope you find it useful:

             

            There are actually three UARTS on the Bay Trail SoC – two HSUARTs that are part of the Serial IO (SIO) block of devices, and one legacy UART, that is part of the Platform Controller Unit (PCU) block of devices.

             

            The HSUART registers are accessed through PCI BARs, whereas the legacy UART uses the legacy COM1 I/O space registers, 3f8h-3ffh.

             

            Whether or not they disable the on-chip HSUARTs is irrelevant, as they don’t use the legacy I/O space addresses for COM1 and COM2.

             

            Although you can disable the HSUARTs with the BCT, the legacy UART cannot be enabled or disabled via the BCT. The legacy UART is actually enabled in coreboot - file coreboot/src/soc/intel/fsp_baytrail/romstage/romstage.c calls function byt_config_com1_and_enable(), which is implemented in file coreboot/src/soc/intel/fsp_baytrail/romstage/uart.c and sets the bit to enable the legacy UART (it’s disabled by default when the chip powers on). This could be replaced by code that initializes COM1 on the Fintek part instead of the UART.

             

            Note that the FSP might also enable the legacy UART internally during the call to FspInitEntry. If so, then it would simply need to be disabled again in the continuation function, which, in coreboot, is function romstage_main_continue() located in file coreboot/src/soc/intel/fsp_baytrail/romstage/romstage.c.

             

            Here is the public datasheet for reference on the various UARTs:

            http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-e3800-family-datasheet.pdf

             

            Best Regards,

            Adolfo