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The display physical interfaces consist of output logic pins that transmit the display data to the associated encoding logic and send data to the display device. These interfaces are digital (MIPI-DSI, DisplayPort, Embedded DisplayPort, DVI and HDMI Interfaces.
These signals are not directly configurable, you configure them through HDMI, DVI, DisplayPort (DP) or Embedded DisplayPort (eDP) ports configuration in the VBIOS.
Please review the document Intel Atom Processor Z3600 and Z3700 Series Datasheet. Table 53 on page 90, Display Physical Interfaces Signal Names, there is more detailed information about these signals.
What tool are you using to configure VBIOS?
What operating system ?
Hi Gabriel Thomas,
Thank you for the quick reply!
In the document you mentioned in your reply, take a look at page 39 and 40 (see pictures). You will see that the signals I mentioned in my request for help is marked with a cross. That means that these signals are multiplexed and may not be available without configuration. In these case they are not available without configuration as they default to the GPIO function at power on. In the EDS documentation the ball listing shows that the DDIO_BKLTCTL signal for example defaults to GPIO_S0_NC.
The cross marked signals below are simply not connected to the balls at power on and needs to be reconfigured by the pad configuration registers. However, every multiplex configuration register is mentioned and documented in the EDS, except the configuration registers for these 10 signals.
As these signals are not available, VBIOS are not able to detect the display devices connected to the DDI ports.
We develop the fastest BIOS int the world for embedded systems. It's a legacy BIOS, doing full POST and initializing all the hardware and yet do the POST under 1 second. We focus on the Atoms and support Z5xx/SCH, N270/945GSE/ICH7, CEDARVIEW and now BAYTRAIL. We use the latest BMP tool for configuring VBIOS on a windows hosted system.
Unfortunately, VBIOS is not available in source code, so the interaction between system BIOS and VBIOS is not good. If we had the opportunity to work with the source code we would be able to contribute with a big improvement in interaction between system BIOS and VBIOS. As we don't do UEFI, we would be the perfect partner for Intel to maintain VBIOS. We have also made major contributions to Open Watcom, the tools used for building VBIOS, so a cooperation would be beneficial for both of us.
Okay, I hope you will be able to help me with this one. If the configuration registers for the signals mentioned was documented, we would not have to bother you with these kind of questions. If you think about it, you have the BWG and EDS for the chipset and still can't do the job. As almost all board applications has display connections, I can't understand why this is leaved out from the documentation.
How are your team doing? No one has contacted me. Is it okay that I send a copy of our communication here to our contractors. They are very driving in this project and want to know how it goes and I have to report the status to them.
The status is that the BIOS works, but many pins used in the design is not connected to the pads. The balls have names with a certain functionality that are connected to various logic on the boards, but the signals are not connected to the balls and needs to be configured.
However, the configuration registers are not documented, so there is no way for me configure the chip to the functionality expected by the board designer.
I ask you what to do, as I think we should solved this together without involving our customer. Or do you think it's better to involve them to get the proper priority for this matter? Our customer are on of the biggest Intel customers in the world and they are very eager on this project. This is a top priority project for this company and there are many peoples involved.
Please, let me know how to proceed.
Well, 3 weeks has passed and your team has not coming up with any information in this matter what so ever. However, I have solved it myself (as usual). It would be more effective if Intel had support that worked. After all, you develop the chips and you should know stuff about them. Any decent engineer is expected to have knowledge of what he or she is doing.
Thank you anyway for all your help. Adolfo did all he could, but failed too as he do not have access to right documentation. Kudos to Adolfo for trying!!!!
Regarding the information missing in EDS, the location of the configuration registers for these pins was in the BWG 1.42. The problem was solved by finding out the function number of the signals and thus simply make a bitwise OR as all the bits except the function number in the registers proved to be correct.
The power on (reset) function numbers defaults to 0, so just making an bitwise OR with the correct function number will suffice. In C syntax, *(IOBASE + DDI0_BKLTCTL) |= FUNCTION_NUMBER;