Please check document #510858: Bay Trail-I SoC External Design Specification For Bay Trail platforms based on the Bay Trail-I SoC,
section 13.1 Register Map, includes a register description. Please let us know if you need additional information about it.
We keep looking for the detailed information requested.
I have received your mail this morning, with document #510858 Bay Trail-I SoC External Design Specification Revision 1.5, July 2013. After checking with your suggested 13.1 section, I still cannot see my required memory register information.
When comparing the new received #510858 and the #538136 Atom Processor E3800 series datasheet on hand, they looks very alike. On #538136 there are some of the memory registers I need on section 12.3 - System Memory Controller (D-unit) Message Registers, but there is no such 12.3 section in #510858.
To be clear I would like to get the location and decriptions of System Memory Controller (D-unit) Message Registers like this one.
FERRNERR (FERRNERR) - the First Error and Next Error register
Would you check if any of Intel documents of E3800 series Processor have description of such registers?