Each port has its own MDC/MDIO or two wire interface bus. However, the MDC/MDIO bus of LAN port 0 may be shared by all ports configured to external PHY operation (MDICNFG.destination set to 1), to allow control of a multi PHY chip with a single MDC/MDIO bus. Reference located in section 220.127.116.11, MDIO/MDC PHY Management Interface.
MDIO operation using a shared bus or a separate bus is controlled by the MDICNFG.Com_MDIO bit, which is loaded from initialization Control 3 EEPROM word following reset. The external port PHY Address is written in the MDICNFG.PHYADD register field, which is loaded from the Initialization Control 4 EEPROM word following reset.
Please refer to the table 8.2.5 MDC/MDIO Configuration Register - MDICCNFG (0x0E04; R/W).
When Interfacing an external SGMII PHY bit defines if MDIO access is routed to the common MDIO port LAN 0, to support multi port external PHYs, or to the dedicated per function MDIO port.
It is important to check the bit 30 (Com_MDIO2), due to this will define the MDIO access routed to the LAN port's MDIO interface or the access to this LAN port routed to LAN port 0 MDIO interface.
I hope this information is useful,