2 Replies Latest reply on Apr 29, 2015 11:51 AM by gabriel.thomas

    I350

    Khasin Community Member

      Hi,

      My name Igor, I am working for Nebbiolo Technology Inc. we are planing to use I350 Ethernet Controller, and I have question about MDIO interface.

      According to  datasheet there is 4 MDIO/MDC interfaces could be connected to external PHYs, but in MDICNFG register description there is only 4 LANs could be addressed,

      and in MDI Control register there is only 5 bits Register address, no PHY address could be set. In MDIO frame does it send PHY address which set in MDICNFG register?

      Also how it select which MDIO interface out of 4 will be used? Does it also based on MDICNFG register field [25:21]?

       

      Regards,

      Igor

        • Re: I350
          jc Brown Belt

          Hello Igor Khasin.

           

          Welcome to Intel® Embedded Community.

          We are checking your thread and will post an update as soon as possible.

           

          Regards.

          Josue.

            • Re: I350
              gabriel.thomas Brown Belt

              Hello Igor,

               

              Each port has its own MDC/MDIO or two wire interface bus. However, the MDC/MDIO bus of LAN port 0 may be shared by all ports configured to external PHY operation (MDICNFG.destination set to 1), to allow control of a multi PHY chip with a single MDC/MDIO bus. Reference located in section 3.7.2.2, MDIO/MDC PHY Management Interface.

               

               

              MDIO operation using a shared bus or a separate bus is controlled by the MDICNFG.Com_MDIO bit, which is loaded from initialization Control 3 EEPROM word following reset. The external port PHY Address is written in the MDICNFG.PHYADD register field, which is loaded from the Initialization Control 4 EEPROM word following reset.

               

              Please refer to the table 8.2.5 MDC/MDIO Configuration Register - MDICCNFG (0x0E04; R/W).

              When Interfacing an external SGMII PHY bit defines if MDIO access is routed to the common MDIO port LAN 0, to support multi port external PHYs, or to the dedicated per function MDIO port.

              It is important to check the bit 30 (Com_MDIO2), due to this will define the MDIO access routed to the LAN port's MDIO interface or the access to this LAN port routed to LAN port 0 MDIO interface.

               

              I hope this information is useful,

               

              Regards,

              Gabriel Thomas.