6 Replies Latest reply on Oct 8, 2015 8:20 AM by Carlos_A

    Cedartrail (D2600/NM10)

    MattB Community Member

      We have an embedded solution using a NM10 and D2600.

       

      We are experiencing issues with RTC time resetting or freezing when the unit is powered on and off.

       

      Not all units are doing this, just some.

       

      We have checked the 32kHz crystal and the VCCRTC and these are all ok.

       

      The problem occurs most the time when power is removed from the unit and we do an "uncontrolled" shutdown.

       

      We came across an Intel document "Next Generation Intel® Atom™ Processor based Mobile Platform  Code named Cedar Trail-M)" (449933) which in section 3.13.4 includes an external circuit which should be included on the NM10 RSMRST input line to control RSMRST signal during powerdown. (RSMRST pulled low before VccSus3_3 drops to 2.1)

       

      In the NM10 datasheet the RSMRST signal is shown in the power on cycle (figure 8-32, 8-33, 8-34, 8-35). None of the shutdown timing charts show the RSMRST signal for the power down sequence.

       

      Does the RSMRST input need to have a hardware control to drive the signal low when before VCCSUS3_3 drops?

        • Re: Cedartrail (D2600/NM10)
          gabriel.thomas Brown Belt

          Hello Mathew,

           

          Welcome to the Intel Embedded Community,

          We are working in your case and we will contact you as soon as possible.

           

           

          Regards,

           

          Gabriel Thomas.

          • Re: Cedartrail (D2600/NM10)
            Carlos_A Brown Belt

            Hello MattB,

             

            Thank you for contacting the Intel Embedded Community.

             

            The suggested RSMRST implementation can be found in section 19.7, on page 247 of the Next Generation Intel(R) Atom(TM) Processor based Desktop [Code named Cedar Trail-D] Platform Design Guide (PDG) For use with the Intel(R) Atom(TM) Processor D2000 Series (Code Named Cedarview-D) and Intel(R) NM10 Express Chipset document # 449934.

             

             

             

            Please note this document is classified as Intel Confidential.

             

             

            By the way, please follow the power sequencing guidelines stated in section 20.8.6.2, on page 283 of this PDG [document # 449934].


            Please let us know if this information is useful to you.


            Best Regards,

            Carlos_A

              • Re: Cedartrail (D2600/NM10)
                MattB Community Member

                Hello Carlos,

                 

                Thank you for the reply.

                 

                The circuit in document 449934 will handle the power up requirement, but I am unclear how this circuit would be able to handle the power down requirement?

                 

                In our design we have implemented the RSMRST signal via a CPLD which controls the delay at startup.

                 

                In document 449933 Section 3.13.6 "Power-Well Isolation Control Strap Requirement" it has an additional circuit which is used to pull RSMRST low as the VccSus3.3 supply turns off.

                 

                Looking at the Intel reference circuit 477527 this seems to implement the circuit you have suggested in Section 19.7 (of 449934) but doesn't take into account the power down issue.

                 

                From what we have seen on our design, if we don't implement the circuit in 449933 3.3.16 then we get massive problems with CMOS corruption and RTC clock issues.

                 

                In document 449933 it states the following:

                "The rising edge of the RSMRST# signal of the chipset must transition from the 20% signal level to 80% and vice-versa in 50 μs or less and the falling edge must transition to 0.8 V or less before VccSus3_3 drops to 2.1 V."

                 

                What I am unclear about is how is the power down requirement handled on the reference design, specifically in the case when the power is removed from the unit in an uncontrolled shutdown?

                 

                Many thanks,

                 

                Matthew

                  • Re: Cedartrail (D2600/NM10)
                    Carlos_A Brown Belt

                    Hello MattB,

                     

                    Thanks for your reply.

                     

                    The Power Management Integrated Circuit (IC) is the device to regulate the sequencing (power up and power down) of your platform. You can confirm this information in Figure 1-1, on page 22 of the PDG document # 449934, which is the proper if your are using an Intel(R) Atom D2600 that is desktop processor.

                     

                    The conditions stated in the documentation are the suggested to the proper functionality of the Intel devices. Due to this fact, any situation out of mentioned in Intel documents is unsupported and undetermined.

                     

                    Please let us know if this information is useful to you.

                     

                    Best Regards,

                    Carlos_A

                      • Re: Cedartrail (D2600/NM10)
                        MattB Community Member

                        Hi Carlos,

                         

                        I am not question the Intel specification (449934), I am questioning why the Intel CedarRock Reference Design (477527) does not align with the Intel datasheet?

                         

                        The Intel reference design includes the 'RSMRST# Generation" circuit (Section 19.7) but it doesn't appear to include the "Power-Well Isolation Control Strap Requirements" (section 19.6).

                         

                        It is not clear to me how the power-well isolation is guaranteed on the Intel Reference Design?

                         

                        Thanks,

                         

                        Matthew

                         

                         

                         

                          • Re: Cedartrail (D2600/NM10)
                            Carlos_A Brown Belt

                            Hello MattB,

                             

                            Thanks again for your reply.

                             

                            It is important to let you know that the Customer Reference Board (CRB) is a device that has been designed at early stages of the platform implementation. So, its schematics [such the document # 477527] omit modifications to the design that reflect the latest corrections to past issues and improvements of the design.

                            Please always follow the latest documents such as the Electrical, Mechanical, and Thermal Specifications (EMTS), Platform Design Guides (PDG) [such the document # 449934] and Datasheets (with addendums)[such the document # 326136 and 326137] since some things have been changed / corrected after the CRB was designed.

                             

                            You can confirm this information in the release dates of the cited documents stated on the first page of them.

                             

                            Please let us know if this information is useful to you.

                             

                            Best Regards,

                            Carlos_A